Sandisk Technologies Inc.

Micron Technology Incorporated

Binoy Jose Panakkal

Gopu S

Bhavadip Bipinbhai Solanki

Rajesh N Gupta

Ganapati Bhat

Lakshmi Sowjanya Sunkavelli

Pawan Negi

Manoj M Shenoy

Subin Cp

When an open block of NAND memory is read, this places the edge word lines under a set of bias conditions that can lead to disturbs. When time tag values are stored on predefined word lines, and the predefined word line is an edge word line, this can degrade not just the user data on the word line, but also the time tag values, leading to a failed bit count spike. To address this problem, a time tag word line shift approach is introduced where, if a predetermined time tag acquisition word line is an edge word line, another word line is instead used to acquire the time tag value.

Time tag word line shift to reduce failed bit count spikes for edge word lines

Embodiments of the disclosed technology relate to the operation of memory devices, and more particularly to sub-block mode (SBM) pre-charge operation sequences. One example embodiment provides a novel logic design of the control circuitry of a memory device using comments/instructions for the control circuitry. By virtue of the features of the disclosed technology, the control circuitry can effect pre-charging of an inner or middle vertical sub-block of a NAND string in a memory array. In some examples the NAND string has at least three vertical sub-blocks of non-volatile memory cells.

Sub-block mode (SBM) pre-charge operation sequences

A memory device includes a wordline zone table that stores information about how wordlines of one or more memory blocks are divided into wordline zones. The wordline zone table also stores a value associated with each wordline zone. When the memory device receives a command, a controller identifies a wordline associated with the command. The controller uses the wordline zone table to determine the wordline zone, and the value, associated with the wordline. The value is stored in a non-data wordline. When a find last good page (FLGP) process is initiated in response to an ungraceful device shutdown (UGDS) event, the controller determines the value stored in the non-data wordline. The controller compares the value in the non-data wordline to the values in the wordline zone table to determine which wordline zone matches the value. The FLPG process is applied to the wordline zone having the matching value.

Using a zone wordline table to initiate a find last good page process

A three tier memory has an upper sub block, a lower sub block, and a middle sub block. In the present disclosure, rather than precharging the upper and lower sub blocks, use is made of the middle sub block using a firmware (FW) scheme. Upon receiving a write request from a host, the FW will route the data to the middle sub block (SB) through reverse order programming (ROP) so that the SBis pre-charged through the source side through the lower sub block (SB). Once the SBis written, data is then routed to the SBand then to the upper sub block (SB). When there is a garbage collection (GC) request, the FW will move the data from the SBand then erase the SB. Then the data moves from the SBand SBis erased. Finally, the data moves from the SBand then SBis erased.

Firmware scheme for 3 tier memories

A measurement circuit may include a transistor having a first terminal, a second terminal, and a third terminal, wherein the first terminal is coupled to a first reference voltage. The measurement circuit may further include a first operational amplifier including a first input coupled to the second terminal of the transistor and an output coupled to the third terminal of the transistor. The first operational amplifier may further include a second input configured to receive a second reference voltage. The measurement circuit may also include a first unity-gain voltage follower including a second operational amplifier having a first input coupled to the first input of the first operational amplifier. Methods of measuring a threshold voltage, semiconductor devices, and electronic systems are also described.

Growing community of inventors

Kerala, India

Binoy Jose Panakkal