Huazhong University of Science and Technology

Binhao Wang

Xiangshui Miao

Hao Tong

Shaojie Long

Provided is a dynamic memory structure and an operating method thereof. The dynamic memory structure includes a write gating device, a read gating device, and a capacitor. A first terminal of the write gating device, a first terminal of the read gating device, and a first terminal of the capacitor are connected together; a second terminal of the write gating device is a data writing end; a second terminal of the read gating device is a data reading end; and a second terminal of the capacitor is a gating end and connected to a word line. The write gating device and the read gating device are both unidirectionally conducted, and conduction modes of the write gating device and the read gating device are both threshold-on. A conduction threshold voltage of the write gating device is less than a conduction threshold voltage of the read gating device.

Method for operating a dynamic memory structure having a write gating device, a read gating device, and a capacitor

Provided is a design method for a threshold switch device, a threshold switch device, and a dynamic memory, relating to the technical field of memories. The design method includes: testing a hold voltage, a low-resistance-state (LRS) resistance, and a threshold voltage of a threshold switch function layer; determining a target hold voltage of a threshold switch device according to the threshold voltage; determining a resistance sum of a top electrode and a bottom electrode of the threshold switch device according to the hold voltage and the LRS resistance of the threshold switch function layer and the target hold voltage of the threshold switch device; and selecting materials and thin film parameters of the top electrode and the bottom electrode according to the resistance sum of the top electrode and the bottom electrode of the threshold switch device, to design the threshold switch device meeting the target hold voltage.

Method for threshold switch device, threshold switch device, and dynamic memory

The invention discloses a three-dimensional 1S1C memory based on a ring capacitor and a preparation method. The memory includes: a horizontal peripheral electrode layer including a first dielectric layer and a first metal electrode layer alternately stacked and grown on a substrate and provided with trenches penetrating in a vertical direction and holes penetrating in the vertical direction, a vertical functional layer, and a capacitive dielectric layer. An annular groove is disposed outside each hole. The annular groove surrounds the holes and vertically cuts off the peripheral electrode layer. The annular groove is evenly filled with a capacitive dielectric layer. A top of the second metal electrode layer is extended to a surface of a topmost first dielectric layer to form a bit line electrode and is connected to a bit line. A region where the second metal electrode layer faces the first metal electrode layer forms a memory cell.

Three-dimensional 1S1C memory based on ring capacitor and preparation method

Disclosed are an OTS-based dynamic storage structure and an operation method thereof. The OTS-based dynamic storage structure includes a plurality of storage units distributed in an array, and each storage unit includes an OTS gating transistor and a storage capacitor. The OTS gating transistor has two states, namely, high resistance state and low resistance state. When the voltage across the OTS gating transistor exceeds the threshold voltage V, the OTS gating transistor is switched from the high resistance state to the low resistance state. When the voltage across the OTS gating transistor in the low resistance state is lower than the holding voltage V, the OTS gating transistor is switched from the low resistance state to the high resistance state.

OTS-based dynamic storage structure and operation method thereof

A method for operating a dynamic memory is provided, and the method includes the following steps. A refresh operation is performed on the dynamic memory according to predetermined interval time T, an operation command is received in real time at the same time, a read operation is performed on a selected memory cell according to position information of the selected memory cell in the operation command when the operation command is received, and state data read in the read operation is temporarily stored in a read buffer. The interval time T is less than time t required for a voltage value of a capacitor in the memory cell to drop to a critical capacitor voltage value for the read operation to correctly read the state data of the memory cell during a write operation. According to operation command type information in the operation command, corresponding operations are performed on the selected memory cell.

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Hubei, China

Binhao Wang