Altera Corporation

The Perkin-elmer Corporation

Binh Vo

Jayabrata Ghosh Dastidar

Adam J Wright

Hung Hing Anthony Pang

Barton G Selby

David Clark

Johan Goudberg

Peter Boyle

Kalyana Ravindra Kantipudi

Paul J Tracy

Souvik Ghosh

Qi Chen

Michael Harms

Ajay Nagarandal

Alok Shreekant Doshi

Kaiyu Ren

Laiq Chughtai

John DiCosola

Seng Yew Lim

Wan-Pin Hung

Sergey Timokhin

Munechika Sakabe

Thomas Schefer

A programmable integrated circuit may contain multiple logic blocks. Computing equipment may be used to run automated tools that process a design for the programmable integrated circuit to perform corresponding circuit tests. A translation tool may translate a transistor-level description of circuitry on the programmable integrated circuit into a gate-level description. A block-level test configuration data generation tool may generate block-level test configuration data files. The test configuration data files may be used as constraints for an automatic test pattern generation tool that produces block-level test vectors. A full-chip propagation tool may use the block-level test vectors, block-level test configuration data files, and full-chip constraints to produce corresponding full-chip test configuration data and full-chip test vectors for testing the integrated circuit. A translation tool may convert the configuration data and test vectors into a tester file.

Automatic test pattern generation system for programmable logic devices

Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.

Functional failure analysis techniques for programmable integrated circuits

A method for generating automatic design characterization patterns for integrated circuits (IC) is provided. The method includes selecting a routing scheme from a file containing the device description of the routings of the IC. The routing scheme may be of a phase locked loop, clock tree, delay element, or input output block in one embodiment. Resource types for the routing scheme are identified and a path is defined, within constraints, between the resources. Once a path is defined, alternate paths are defined by retracing the path within constraints from an end of the path to the beginning of the path. An alternative path is then built and the alternative path shares a portion of the path previously defined. A computing system providing the functionality of the method is also provided.

Method and system for semiconductor device characterization pattern generation and analysis

Programmable circuits have a programmable interconnect structure that connects programmable circuit elements. Tests patterns can be automatically generated for the programmable circuit elements and interconnections on a programmable circuit. A connectivity graph represents programmable interconnections and functions as nodes. Tests routes are generated that connect the nodes in the connectivity graph between control points and observation points on the programmable circuit. The routes are grouped into configuration patterns that can be tested in one test cycle. Test vectors are then applied to the routes to determine if the interconnects and circuit functions are operable. Systems and methods of the present invention automatically create test patterns for a programmable circuit to reduce engineer time. The present invention also reduces test time and resources by increasing the number of interconnections and circuit elements tested in each configuration pattern.

Techniques for automatically generating tests for programmable circuits

The present invention relates to the electrophoretic separation of bio-organic molecules using a slab gel electrophoresis apparatus having a pair of spaced, confronting plates defining a multi-lane separation zone adapted to hold a separation medium and an upper loading zone. In one aspect of the invention, at least one of the plates is shaped to provide an expanded loading zone. The plate-to-plate distance within the expanded loading zone is greater than the plate-to-plate width within the separation zone. In another aspect of the invention, a comb is provided with each tooth having a gradual taper beginning at a support member and extending along most of the tooth's longitudinal axis, and a sharp taper beginning immediately beyond the gradual taper and extending to the end of the tooth. In a related aspect of the invention, a method is provided wherein a comb is inserted into the loading zone so that the teeth penetrate an upper portion of the separation medium, thereby forming a series of fluid-tight, elongate sample-loading apertures of substantially rectangular cross-section having a plate-to-plate width greater than that of the inter-plate distance in the separation zone. Methods of separating biomolecule analytes for optimized resolution and increased base reads are also disclosed.

Electrophoresis method and apparatus for separating bio-organic molecules

The present invention relates to the electrophoretic separation of bio-organic molecules using a slab gel electrophoresis apparatus having a pair of spaced, confronting plates defining a multi-lane separation zone adapted to hold a separation medium and an upper loading zone. In one aspect of the invention, at least one of the plates is shaped to provide an expanded loading zone. The plate-to-plate distance within the expanded loading zone is greater than the plate-to-plate width within the separation zone. In another aspect of the invention, a comb is provided with each tooth having a gradual taper beginning at a support member and extending along most of the tooth's longitudinal axis, and a sharp taper beginning immediately beyond the gradual taper and extending to the end of the tooth. In a related aspect of the invention, a method is provided wherein a comb is inserted into the loading zone so that the teeth penetrate an upper portion of the separation medium, thereby forming a series of fluid-tight, elongate sample-loading apertures of substantially rectangular cross-section having a plate-to-plate width greater than that of the inter-plate distance in the separation zone.

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San Jose, CA, United States of America

Binh Vo