Advanced Micro Devices Corporation

Other

Fujitsu Corporation

Fasl LLC

Google Inc.

Leland Stanford Junior University

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Spansion LLC.

San Diego State University Research Foundation

Cypress Semiconductor Corporation

Binh Quang Le

Pau-Ling Chen

Shane Charles Hollmer

Lee Edward Cleveland

Darlene G Hamilton

Pauling Chen

Shoichi Kawamura

Kazuhiro Kurihara

Michael S Chung

Chung-You Hu

Masaru Yano

Santosh K Yachareni

Joseph G Pawletko

Vincent C Leung

Sameer S Haddad

Yu Nan Sun

Chi K Chang

James M Hong

Mike Van Buskirk

Mark W Randolph

Michael Allen Van Buskirk

Narbeh Derhacobian

Edward Hsia

Edward Franklin Runnion

Michael S C Chung

Michael Achter

Cathy Thuvan Ly

Nian Niles Yang

Johnny C Chen

Tien-Chun Yang

Colin Stewart Bill

Wei Zheng

Yi He

Ravi Prakash Gutala

Aaron Lee

Scott M Petry

Zhizheng Liu

Ming-Huei Shieh

Elisa Vianello

Nancy S Leong

Kenneth K Okumura

Guowei Wang

Tiao-Hua Kuo

Michael A VanBuskirk

Shigekazu Yamada

Michael Van Buskirk

Jonathan S Su

Michael John Oswall

Subhasish Mitra

Sachit Chandra

Eric M Ajimine

Roger Tsao

Ken Tanpairoj

Etienne Nowak

Andrew Yang

Alexius H Tan

Philip Wong

Chen Pauling

Erik Chen

Pau-Lin Chen

Adam Dawes

Joseph Green

Lisa Lund

Fan Tony Wu

Paul-Ling Chen

Nancy Leong

Johnny Chen

An apparatus and system are described to provide an in-memory computing non-volatile flash memory cell array used in a neural network. Each cell includes a Resistive RAM memory (RRAM) and a physical resistor formed from a high resistive material. The RRAM is programmed to either an on or off state in which the resistance is respectively significantly less or more than the resistor to permit the RRAM to act as a switch and allow for in-situ training. Multi-bit RRAM cells contain multiple RRAMs, each of which is connected to a resistor having a different resistance and read using the same input line. The resistors are formed from the same material as the resistor in the analog-to-digital converter used to read the array.

Synaptic array for field-training-capable in-memory computing using non-volatile memory technologies

The present disclosure relates to a method of programming resistive memory cells of a resistive memory, the method comprising: applying, by a programming circuit based on a first target resistive state, an initial resistance modification to a first cell of the resistive memory to change its resistance from an initial resistive state to a first new resistance; comparing, by the programming circuit, the first new resistance of the first cell with a resistance range of the first target resistive state and with a target resistance range associated with the first target resistive state; and if it is determined that the first new resistance is outside the resistance range of the target resistive state and inside the target resistance range, applying by the programming circuit one or more further resistance modifications to the first cell to increase or decrease its resistance.

Circuit and method for programming resistive memory cells

Disclosed are systems and methods for providing transport layer encryption with an intermediate electronic message managing service interposed in a message path of an electronic message to be sent from a sending server to an intended receiving server across a computer network. To implement TLS in such a managed e-mail services context, given that a managed e-mail service is inserted into the message delivery path, the transport layer security protocols are simultaneously established along both the link from the sending server to the managed e-mail service and from the receiving server to the managed e-mail service, with the managed e-mail service providing a 'proxy' connection for communication between the sending server and the receiving server.

TLS encryption in a managed e-mail service environment

A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

High performance flash memory device capable of high density data storage

A method for a memory redundancy, including a memory array typically having a plurality of columns (e.g., bit lines) of memory cells, and identifying a particular (e.g., defective) column of the memory array and further defining a redundancy window by selecting a group of adjacent columns including the defective column. The number of columns in the group of selected columns may be equal to the number of columns in a redundancy array that is coupled to the memory array. The redundancy array is used for storing information that would have been otherwise stored in the memory cells in the redundancy window. The selected group includes at least one column on one side of the defective column and another column on the other side of the defective column. Typically, there will be multiple columns on each side of the defective column.

Method and system for defining a redundancy window around a particular column in a memory array

A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.

Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference

An erase methodology of flash memory cells in a multi-bit memory array with bits disposed in normal and complimentary locations. An erase verify of bits in the normal locations is performed and if a bit in the normal location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the normal bit and the complimentary bit. An erase verify of bits in the complimentary locations is performed and if a bit in the complimentary location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the complimentary and the normal bit locations. If the bits pass the erase verify, the bits are subjected to a soft programming verify. If the bits are overerased and if the soft programming pulse count has not been reached a soft programming pulse is applied to the overerased bit.

Erase method for a dual bit memory cell

A bandgap reference circuit includes a current generation circuit connected to a voltage generation circuit connected to a smart clamping circuit, and a discharge circuit connected to the current generation circuit and the voltage generation circuit. The discharge circuit initially discharges a potential in the current and voltage generation circuits to improve repeatability. A start circuit within the current generation circuit then initializes the reference output at about the supply voltage to improve the speed and settling time of the output signal. The current generation circuit sources a current to the voltage generation circuit that translates the current having a positive function of temperature +Tinto a reference voltage. The smart clamping circuit further generates a clamping voltage having a negative function of temperature &#x2212;Tand a load resistance. The clamping voltage and the load resistance are applied across the reference voltage quickly reducing the reference voltage particularly at high temperatures and during start-up to a final level, thereby producing a fast and stable reference voltage.

Fast bandgap reference circuit for use in a low power supply A/D booster

A cascode amplifier circuit which generates a fast, stable and accurate bit line voltage is disclosed. According to one exemplary embodiment, the cascode amplifier circuit comprises a transistor having a source connected to a bit line voltage and a drain connected to an output voltage. The cascode amplifier circuit also comprises a differential circuit having an inverting input connected to the bit line voltage, a non-inverting input connected to a reference voltage, and an output connected to a gate of the first transistor. The operation of the transistor and the differential circuit generate a fast, stable the accurate bit line voltage.

Cascode amplifier circuit for generating and maintaining a fast, stable and accurate bit line voltage

Flash memory array systems and methods are disclosed for producing a regulated boosted word line voltage for read operations. The system comprises a multi-stage voltage boost circuit operable to receive a supply voltage and one or more output signals from a supply voltage detection circuit to generate the boosted word line voltage having a value greater than the supply voltage. The voltage boost circuit comprises a precharge circuit and a plurality of boost cells connected to a common node of the boosted word line, and a timing control circuit. The stages of the plurality of boost cells are coupled in series for charge sharing between the stages, and couple a predetermined number of boost cells to the boosted word line common node to provide an intermediate voltage to the boosted word line during the pre-boost timing, thereby anticipating a final boosted word line voltage provided during the boost timing. The voltage boost circuit is operable to receive the one or more output signals from the supply voltage detection circuit and alter a boost gain of the multi-stage voltage boost circuit based on the one or more output signals, thereby causing the boosted word line voltage to be substantially independent of the supply voltage value.

Fast, accurate and low power supply voltage booster using A/D converter

A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.

Non-volatile memory read circuit with end of life simulation

A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

Pre-charge method for reading a non-volatile memory cell

According to one exemplary embodiment, a buffer circuit is configured to receive a supply voltage and an input reference voltage, the buffer circuit has a first FET operating in saturation region where the source of the first FET is coupled to the output reference voltage. The first FET can be configured, for example, as an open-loop voltage follower and, by way of example, a first resistor can be used to couple the source of the first FET to the output reference voltage. A tracking circuit is connected to the buffer circuit. The tracking circuit comprises a second FET also operating in saturation region where the drain of the second FET is coupled to the output reference voltage. Both the first and second FETs can be, for example, depletion mode transistors.

Buffer driver circuit for producing a fast, stable, and accurate reference voltage

Cascode amplifier circuit for producing a fast, stable and accurate bit line voltage

A selection circuit for sensing current in a target cell during a memory read operation is disclosed. According to one embodiment, the selection circuit comprises a sensing circuit selector connected to a sensing circuit and a ground selector connected to ground. The ground selector connects a first bit line of the target cell to ground, and the sensing circuit selector connects a second bit line of the target cell to the sensing circuit. The sensing circuit selector also connects a third bit line of a first neighboring cell to the sensing circuit. The first neighboring cell shares the second bit line with the target cell.

Selection circuit for accurate memory read operations

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San Jose, CA, United States of America

Binh Quang Le