Intel Corporation

Binh Q Pham

Christopher B Wilkerson

Ren Wang

Robert G Blankenship

Raanan Sade

Andrew J Herdrich

Anil Vasudevan

Vedaraman Geetha

Shrikant M Shah

Chyi-Chang Miao

Venkata Krishnan

Marshall A Millier

Olivier Serres

David Pardo Keppel

Jared Warner Stark, Iv

Patrick Lu

Robert Valentine

Mark Jay Charney

Zeev Sperber

Christopher J Hughes

Amit Gradstein

Alexander F Heinecke

Simon Rubanovich

Menachem Adelman

Alaa R Alameldeen

Zeshan A Chishti

Zhe Wang

Samantika S Sury

Evangelos Georganas

Barukh Ziv

Mitchell Diamond

Farah E Fargo

Shobha Vissapragada

Chen Dan

Examples described herein relate to a computing system supporting custom page sized ranges for an application to map contiguous memory regions instead of many smaller sized pages. An application can request a custom range size. An operating system can allocate a contiguous physical memory region to a virtual address range by specifying a custom range sizes that are larger or smaller than the normal general page sizes. Virtual-to-physical address translation can occur using an address range circuitry and translation lookaside buffer in parallel. The address range circuitry can determine if a custom entry is available to use to identify a physical address translation for the virtual address. Physical address translation can be performed by transforming the virtual address in some examples.

Programmable address range engine for larger region sizes

Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.

Matrix transpose and multiply

In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

Branch prediction based on coherence operations in processors

Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

Method and system for performing data movement operations with read snapshot and in place write update

A processor includes a translation lookaside buffer (TLB) to store a TLB entry, wherein the TLB entry comprises a first set of valid bits to identify if the first TLB entry corresponds to a virtual address from a memory access request, wherein the valid bits are set based on a first page size associated with the TLB entry from a first set of different page sizes assigned to a first probe group; and a control circuit to probe the TLB for each page size of the first set of different page sizes assigned to the first probe group in a single probe cycle to determine if the TLB entry corresponds to the virtual address from the memory access request.

Valid bits of a translation lookaside buffer (TLB) for checking multiple page sizes in one probe cycle and reconfigurable sub-TLBS

An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.

Method and apparatus for multi-level memory early page demotion

Systems, methods, and apparatuses relating to circuitry to accelerate store processing are described. In one embodiment, a processor includes a (e.g., L1) cache, a fill buffer, a store buffer, and a cache controller to allocate a first entry of a plurality of entries in the fill buffer to store a first storage request when the first storage request misses in the cache, send a first request for ownership to another cache corresponding to the first storage request, detect a hit in the cache for a second storage request, update a globally observable buffer to indicate the first entry in the fill buffer for the first storage request is earlier in program order than the second storage request in the store buffer, allocate, before the second storage request is removed from the store buffer, a second entry of the plurality of entries in the fill buffer to store the third storage request when the third storage request misses in the cache, send a second request for ownership to another cache corresponding to the third storage request, and update the globally observable buffer to indicate the second entry in the fill buffer for the third storage request is later in program order than the second storage request in the store buffer.

Apparatuses, methods, and systems to accelerate store processing

Method, system, and apparatus for leveraging non-uniform miss penalty in cache replacement policy to improve performance and power in a chip multiprocessor platform is described herein. One embodiment of a method includes: determining a first set of cache line candidates for eviction from a first memory in accordance to a cache line replacement policy, the first set comprising a plurality of cache line candidates; determining a second set of cache line candidates from the first set based on replacement penalties associated with each respective cache line candidate in the first set; selecting a target cache line from the second set of cache line candidates; and responsively causing the selected target cache line to be moved from the first memory to a second memory.

Method and system for leveraging non-uniform miss penality in cache replacement policy to improve processor performance and power

Growing community of inventors

Hillsboro, OR, United States of America

Binh Q Pham