Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Binh Nguyen

John P Franz

John Norton

Joseph R Allen

Melvin K Benedict

Vincent Hung Nguyen

Thomas Robert Bowden

Kevin B Leigh

Brian T Purcell

Barry S Basile

William C Hallowell

Chanh V Hua

Raghavan V Venugopal

Alan B Doerr

John D Nguyen

Thomas D Rhodes

James R Duncan

Christoph L Schmitz

Nicholas Mark Hawkins

Wayne Hsu

Allen B Doerr

A thermal management assembly in accordance with one example may include a first thermal management member that includes a first main region that is continuous, a first connection region that is discontinuous, and a first top side. The thermal management assembly may also include a second thermal management member that includes a second main region, a second connection region, and a second top side. The second main region and the second connection region are continuous. The thermal management assembly may further include a connection member to couple the first thermal management member and the second thermal management member to a memory device via the first connection region and the second connection region. The first top side and the second top side are substantially level with a top side of the memory device in a horizontal direction when the first thermal management member and the second thermal management member are coupled to the memory device.

Thermal management assembly

An example device may include processing circuitry and a management controller. The processing circuitry may include a communications interface that includes a first register and a second register. The first register may include a freshness bit and a number of first data bits. The second register may include a number of second data bits that correspond, respectively, to the first data bits. The processing circuitry may write variously to the first data bits in response to detected events, set the freshness bit in response to the management controller reading the first data bits, and reset the freshness bit if any of the first data bits are written to. The management controller may read the first data bits, perform predetermined processing based thereon, write to the second data bits based on the predetermined processing, and request a register transfer. The processing circuitry may, in response to the management controller requesting the register transfer, transfer values of the second data bits to their respectively corresponding first data bits if and only if the freshness bit is currently asserted.

Register-based communications interface

Embodiments provide apparatuses and systems in which slave power sequencers share a command bus and power sequence respective power groups through power sequence states of a power sequencing protocol in response to commands on the command bus. In some examples, a system may include a master power sequencer to output onto a command bus a command to perform a power sequencing protocol for transitioning the system from a first power state to a second power state, and a plurality of slave power sequencers sharing the command bus, each slave power sequencer to power sequence a respective power group to a next power sequence state in response to the command. Other examples are described and claimed.

Power sequencing by slave power sequencers sharing a command bus

During runtime of a system, a memory controller is caused to relinquish control of a memory module that includes a volatile memory and a non-volatile memory. After the triggering, an indication is activated to the memory module, the indication causing a backup operation in the memory module, the backup operation being controlled by an internal controller in the memory module, and the backup operation involving a transfer of data from the volatile memory to the non-volatile memory in the memory module.

Runtime backup of data in a memory module

In accordance with embodiments, a system includes a plurality of component slots and at least one indicator associated with each of said slots. The system also includes a controller coupled to the indicators. The indicators selectively provide installation guidance of components into said slots based on signals from the controller.

Component installation guidance

In accordance with the present technique, a system and method for configuring pins of an input/output (I/O) card in a host system are provided. The method includes reading configuration information from a card field replaceable unit memory and reading system configuration information from a system field replaceable unit memory. Additionally, the method includes configuring pins of a system logic of the host system to be compatible with the I/O device of the I/O card, and configuring pins of an I/O device on the I/O card to in turn configure the pins of the I/O card with a configuration setting compatible with the host system.

Reconfigurable I/O card pins

Growing community of inventors

Houston, TX, United States of America

Binh Nguyen