Huawei Technologies Co., Limited

Bingxin Li

Christian Grewing

Anders Emericks

Anders Jakobsson

Ola Pettersson

Chen Xiao Wang

Jinming Wang

Cheng Zhang

Fuquan Zhang

Chunyuan Ma

Liang Rong

Chen Wang

An interdigital capacitor and a multiplying digital-to-analog conversion circuit, where the interdigital capacitor includes at least one first metal layer. The following components are disposed in each first metal layer: a first electrode; at least one first finger metal connected to the first electrode; a second electrode; and a plurality of second finger metals connected to the second electrode, and at least one third finger metal connected to the second electrode. The at least one first finger metal is alternately disposed with the plurality of second finger metals to form capacitors, and the at least one third finger metal is a dummy finger metal.

Interdigital capacitor and multiplying digital-to-analog conversion circuit

A signal processing arrangement for a transmitter includes an in-phase modulator configured to receive an in-phase signal (I) and configured to modulate the in-phase signal (I); a quadrature modulator configured to receive a quadrature signal (Q) and configured to modulate the quadrature signal (Q); an in-phase demodulator configured to demodulate the modulated in-phase signal (I) and to output a demodulated in-phase signal (I); a quadrature demodulator configured to demodulate the modulated quadrature signal (Q) and to output a demodulated quadrature signal (Q); an in-phase harmonic filter configured to perform a filtering on harmonics in the demodulated in-phase signal (I) and to output an in-phase digital signal (I); and a quadrature harmonic filter configured to perform a filtering on harmonics in the demodulated quadrature signal (Q) and to output a quadrature digital signal (Q).

Signal processing arrangement for a transmitter

Embodiments of the present invention provide a receiver and a wireless communications apparatus. The receiver includes: an attenuation circuit, configured to receive an input signal, and obtain a first signal according to the input signal; a low-noise amplification circuit, configured to receive the first signal, and obtain a second signal according to the first signal; an orthogonal down-frequency conversion circuit, configured to receive the second signal, and process the second signal to obtain an output signal; and a control circuit, configured to separately control the attenuation circuit and the low-noise amplification circuit according to power of an interference signal included in the output signal, so as to determine whether the attenuation circuit attenuates the input signal and whether the low-noise amplification circuit amplifies the first signal.

Receiver and wireless communications apparatus

A method and apparatus for generating a carrier frequency signal is disclosed. The method includes generating a first frequency signal; injecting a modulation signal at a first point of the two-point modulation architecture; generating a second frequency signal from the modulation signal; introducing the second frequency signal by mixing the first frequency signal and the second frequency signal to generate a mixed frequency signal and outputting the carrier frequency signal selected from the mixed frequency signal.

Method and apparatus for generating a carrier frequency signal

A Digital Calibration System for a Phase Locked Loop includes a Tuning Voltage Controller configured to set the tuning voltage to a value; a Phase Difference Quantizer configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; a Digital Controller configured to receive the phase difference of the PDQ and control a coarse tuning signal such that an average phase difference of the PDQ is 0; and a Frequency Calibration Logic configured to calibrate the feedback signal in response to the output of the DC.

System and method for calibrating output frequency in phase locked loop

A method and a device for determining closed loop bandwidth characteristic of a Phase Locked Loop (PLL) () comprising a voltage controlled oscillator (VCO) () controlled by means of a tuning voltage (V) is disclosed. An embodiment of the invention compares the VCO tuning voltage (V) to a low threshold voltage (V) and a high threshold voltage (V), creating an oscillation of the VCO tuning voltage by offsetting the divider value such that the PLL () forces the tuning voltage (V) towards the high threshold voltage (V) when the low threshold voltage (V) is reached, and offsetting the divider value such that said PLL () forces the tuning voltage (V) towards the low threshold voltage (V) when the high threshold voltage (V) is reached, measuring the period of the oscillation between the high and the low threshold voltage of the VCO tuning voltage by counting the number of cycles of a reference clock signal (clk), and comparing the number of reference clock cycles to a reference number of clock cycles to determine the relative loop bandwidth of the PLL ().

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Kista, Sweden

Bingxin Li