Intel Corporation

International Business Machines Corporation

Binglong Zhang

Chia-Hong Jan

Lawrence N Brigham

Dung Q Nguyen

David R Terry

Steven J Battle

Saiful Islam

Sam G Chu

Howard Lawrence Levy

Roland Pang

An approach is provided in which a system writes a set of data into a register file entry that includes a first memory array and a second memory array. The register file entry also includes a set of first write ports corresponding to the first memory array and a set of second write ports corresponding to the second memory array. The system configures a selection bit based on determining that a selected one of the set of first write ports is utilized to store the set of data in the first memory array. In turn, the system reads the set of data out of the first memory array based on the configured selection bit.

Implementing write ports in register-file array cell

A device and method to detect and correct for clock duty cycle skew in a high performance microprocessor having a very high frequency clock. The device includes a delay chain circuit to delay the clock signal and to determine the presence of clock duty cycle skew. The device uses simple latches, flops, and phase-detectors to compare and identify the nature of the clock duty cycle skew. Simple logic is employed to measure and determine the amount and direction of de-skew to apply to the clock signal. After the de-skew operation, the clock duty cycle cycles used to control the execution of the microprocessor are of a more uniform time duration.

Method and apparatus for detecting and correcting clock duty cycle skew in a processor

A polysilicon/amorphous silicon composite layer for improved linewidth control in the patterning of gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The formation of a composite polysilicon/amorphous silicon gate in an integrated circuit gives the device the electrical performance and doping qualities of a polysilicon gate and also gives the device the smoothness of an amorphous silicon gate which improves line definition during gate patterning.

Polysilicon/amorphous silicon composite gate electrode

A device and method to detect and correct clock duty cycle skew detected in high performance microprocessor having a very high frequency clock. The device relies on a delay chain circuit to delay the clock signal and determine the presence of clock duty cycle skew. The device uses simple latches, flops and phase-detectors to compare and identify the nature of the clock duty cycle skew. Simple logic is then employed to measure and determine the amount and direction of de-skew to apply to the clock signal. After the de-skew operation, the clock duty cycle cycles used to control the execution of the microprocessor are of uniform time duration.

Method for correcting clock duty cycle skew by adjusting a delayed clock signal according to measured differences in time intervals between phases of original clock signal

A differential bus having a controllable differential signal development rate. A differential signal development rate control circuit is provided to control the development rate of a differential signal on a differential bus.

Growing community of inventors

Austin, TX, United States of America

Binglong Zhang