Freescale Semiconductor,inc.

Nxp Usa, Inc.

Bingkun Liu

Huangsheng Ding

Yang Liu

A system having master and slave devices and communicating over an I2C bus has SDA and a SCL lines that are normally high unless a device pulls the voltage of the line Low. Normal data signals on the SDA line are set during the low phase of the clock signals on the SCL line and transferred to a receiver during the high phase of the clock signals. A slave device provides an alert signal on the SDA line during the low phase of the clock signals to send an alert signal to the master device. The alert signal may be a pulse signaling the slave device wakeup or a pulse pattern identifying the alerting slave device.

Slave device alert signal in inter-integrated circuit (I2C) bus system

A compound USB device has a controller and a N+1 component USB devices. Each component USB device Cis assigned Eendpoints, where&#x2266;i&#x2266;N and where each component USB device is assigned at least as many endpoints as required by its functionality. At least one component USB device is assigned the maximum number endpoints. At least one other component USB device is assigned the minimum number of endpoints, which is less than the maximum. The controller includes a RAM-share subsystem with a RAM module. The RAM module includes a USB RAM segment that has a buffer descriptor (BD) table and an endpoint data buffer. The BD table includes a corresponding entry for each assigned endpoint. At least a portion of the USB RAM segment is assigned for non-USB uses.

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Suzhou, China

Bingkun Liu