Arm Limited

Lightspeed Semiconductor Corporation

Bingda Brandon Wang

Kostadin Gitchev

Robert Olah

Eric T West

George Shing

Puneet Sawhney

Chit-Ah Mak

Vikas Mishra

An on-chip data processing apparatus has an operating supply voltage selected from a range of supply voltages and has voltage level detection circuitry configured to determine the level of the operating supply voltage. The voltage level detection circuitry comprises adaptive circuitry responsive to a variation in the reference voltage. Phase lock loop circuitry is configured to generate a source clock signal from the operating supply voltage, to receive the voltage level selection signal, to select a target frequency for the source clock signal in dependence on the voltage level selection signal, and to phase lock the source clock signal on the target frequency. Initialization circuitry is configured to initialize the on-chip data processing apparatus for data processing in dependence on the level of said operating supply voltage after the phase lock loop circuitry has phase locked the source clock signal on the target frequency.

Self-initializing on-chip data processing apparatus and method of self-initializing an on-chip data processing apparatus

A differential data strobe receiver is provided which is configured to receive a differential data strobe signal at a first strobe input and a second strobe input, wherein transitions of the differential data strobe signal indicate sample points for an associated data signal. The differential data receiver is configured to identify the transitions of the differential strobe signal by differentially comparing values of the differential strobe signal received at the first strobe input and the second strobe input. The differential data strobe receiver comprises strobe gating circuitry configured to generate a strobe gating signal, wherein the associated data signal can only be sampled in dependence on the differential data strobe signal when the strobe gating signal is asserted and strobe input termination circuitry configured selectively to provide a first termination connection for the first strobe input and a second termination connection for the second strobe input. The differential data strobe receiver is configured, prior to receiving the differential data strobe signal in association with the associated data signal, to participate in an initial gate training process to determine a gating delay used to phase align the strobe gating signal with respect to the differential data strobe signal and the strobe input termination circuitry is configured to provide an asymmetric configuration of the first termination connection and the second termination connection during the initial gate training process.

Apparatus and method for receiving a differential data strobe signal

An integrated circuit is disclosed that comprises: a core comprising logic circuitry: a plurality of interface devices for transmitting signals to and from the processing core, the plurality of interface devices comprising two types of interface devices: one type being a power interface device for delivering power to the core; and a second type being a signal interface device for transmitting data signals between the core and devices external to the integrated circuit; wherein the plurality of interface devices are arranged in two rows, an outer row towards an outer edge of the core and an inner row within the outer row closer to a centre of the core the inner row comprising one of the two types of interface devices and the outer row comprising an other of the two types of interface devices.

Area efficient arrangement of interface devices within an integrated circuit

A system, method and computer program product are provided for determining routing of data paths in interconnect circuitry for an integrated circuit. The method includes the steps of defining a plurality of cells to be provided along the wide interface of the circuitry, further devices being associated with at least one of the cells, and defining the circuitry as an array of blocks formed in rows and columns, with each cell abutting one of the columns. The method includes the steps of: providing a predetermined set of tiles, each tile providing a predetermined wiring layout, and for each block, applying predetermined rules to determine one of the tiles to be used to implement that block, where the rules take into account the location of the block in the array and any association between the further devices and the cells.

Method, system and computer program product for determining routing of data paths in interconnect circuitry providing a narrow interface for connection to a first device and a wide interface for connection to a distributed plurality of further devices

An integrated circuit is provided with a power domain which can be selectively powered-up or powered-down. An output circuitry serving to buffer a signal generated by the core circuitry within such a power domain has its own output power supply voltage. An adaptive voltage sensing circuit senses when the core power supply voltage to the core circuitry falls below a threshold level and generates a voltage-low signal. If output signal retention has been preselected to be active for the output signal concerned, then the output circuitry responds to the voltage-low signal by maintaining the output signal state (output signal driven low, output signal driven high or output signal in a high impedance drive state). The retention mode is preselected by a pulse with its value stored within a mode latch indicating whether or not retention is required. Thus, when the adapted voltage sensing circuitry itself senses the voltage level for the core circuitry falling below the threshold, it activates the retention operation.

Maintaining output I/O signals within an integrated circuit with multiple power domains

A differential receiver having a pair of cross-coupled signal conditioning devices improves transition time and data signal integrity. In an embodiment, the differential receiver includes two signal input nodes and a plurality of transistors, and two signal output nodes. The pair of cross-coupled signal conditioning devices are coupled to the transistors and function to reduce voltage swing between the two output nodes, thereby keeping the transistors in a saturation region.

Growing community of inventors

Milpitas, CA, United States of America

Bingda Brandon Wang