Mediatek Corporation

Bing-Yu Hsieh

Chih-Ching Chen

Shu-Hung Chou

Hsiang-Hui Chang

Jing-Hong Conan Zhan

Kuo-Jung Lan

Ming-Jiou Yu

Chia-Wei Liao

Ping-Ying Wang

Yuh Cheng

Hong-Ching Chen

Ling-Wei Ke

Kuan-Hua Chao

Chia-Hua Chou

Wei-Hsuan Tu

Meng-Hsueh Lin

Jong-Woei Chen

Tai Yuan Yu

Jung-Feng Ho

An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.

Error protection method, TDC module, CTDC module, all-digital phase-locked loop, and calibration method thereof

Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error or a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.

Error compensation method, digital phase error cancellation module, and ADPLL thereof

For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

All-digital phase-locked loop, loop bandwidth calibration method, and loop gain calibration method for the same

An automatic power control system, an automatic power control method, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count. The controller, coupled to the counter, disables the counter when the digital data is invalid. The comparator, coupled to the down sampling circuit, compares the representation data with predetermined target data to generate error data. The digital-to-analog converter, coupled to the comparator, converts the error data to analog to generate the control signal.

Automatic power control system for optical disc drive and method thereof

An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.

A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.

PLL with loop bandwidth calibration circuit

An automatic power control system, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count. The controller, coupled to the counter, disables the counter when the digital data is invalid. The comparator, coupled to the down sampling circuit, compares the representation data with predetermined target data to generate error data. The digital-to-analog converter, coupled to the comparator, converts the error data to analog to generate the control signal.

An apparatus for detecting the wobble carrier frequency of an optical disk is disclosed. The apparatus comprises an offset canceller, a binary conversion module, an adjustable band pass filter, and a frequency detection module. The offset canceller cancels the direct current offset of a first wobble signal to obtain a second wobble signal. The binary conversion module converts the second wobble signal to a binary data stream. The adjustable band pass filter passes only an adjustable frequency range of the binary data stream to generate a filtered signal, wherein the center frequency of the adjustable frequency range is sequentially adjusted. The frequency detection module then determines maximum amplitude of the filtered signal, and determines the center frequency of the adjustable frequency range according to which the filtered signal with the maximum amplitude is generated, wherein the wobble carrier frequency is the center frequency corresponding to the maximum amplitude.

Apparatus for detecting the wobble carrier frequency of an optical disk and method for same

A method for controlling a specific output power level emitted from a laser diode (LD) in an optical pick-up head unit (OPU) is disclosed. The LD is configured to provide a plurality of output power levels for accessing/recording an optical disc. The method includes: determining a specific power control value according to a first output power level, a second output power level, a first power control value of the first output power level, and the specific output power level, wherein the first output power level is less than the specific output power level and greater than the second output power level; and driving the LD to emit the specific output power level according to the specific power control value, the first power control value, and a second power control value of the second output power level.

Power control system and related method

The invention provides an apparatus for demodulating an Address In Pre-groove (ADIP) symbol. The ADIP symbol is carried by a wobble signal of an optical disk and comprises a series of ADIP bits permuted according to one of a plurality of permutation patterns to make up the ADIP symbol. A wobble extraction module extracts the wobble signal from the optical disk. A reference wobble generator generates a reference wobble with the same frequency and phase as a fundamental frequency and phase of a positive wobble cycle of the wobble signal. A waveform difference measurement module then measures a difference between the wobble signal and the reference wobble to obtain a series of difference measurement values respectively corresponding to the ADIP bits. A pattern matching module then compares probabilities of the permutation of the ADIP bits agreeing with each of the permutation patterns according to the difference measurement values to determine the ADIP symbol.

Apparatus for demodulating address in pre-groove symbols and apparatus for decoding pre-pit symbols

The invention provides a wobble detection circuit. An exemplary embodiment of the wobble detection circuit comprises an automatic gain control module, an analog to digital converter, a digital band pass filter, and a digital band pass filter. The automatic gain control module amplifies a first input signal and a second input signal detected by a pickup head to the same magnitude to obtain a first amplified signal and a second amplified signal. The adder then subtracts the second amplified signal from the first amplified signal to obtain an analog wobble signal. The analog to digital converter then converts the analog wobble signal to a first digital wobble signal. Finally, the digital band pass filter accepts frequency components of the first digital wobble signal within a pass band and rejects frequency components of the first digital wobble signal outside the pass band to obtain a second digital wobble signal.

Wobble detection circuit and method for processing wobble signals

A pre-pit signal generating device includes: a first slicer for generating a sliced signal corresponding to a push-pull signal based on a first reference level; a duty ratio controller coupled to the first slicer for adjusting the first reference level or the push-pull signal to control a duty ratio of the sliced signal to a predetermined ratio; a reference level generator coupled to the duty ratio controller for generating a second reference level corresponding to the first reference level; and a second slicer coupled to the reference level generator for generating a first pre-pit signal corresponding to the push-pull signal based on the second reference level.

Duty ratio control apparatus for pre-pit detection or header detection of an optical storage medium

A clock rate adjustment apparatus and a method for adjusting a clock rate of a clock for an optical storage system are provided. The clock rate adjustment apparatus comprises an indication provider, a throughput rate detector, and a clock generator. The method performs the following steps. The indication provider generates an indicatory signal indicating a state of the optical storage system. The throughput rate detector generates a control signal in response to the indicatory signal. The clock generator generates the clock at the clock rate in response to the control signal. The clock rate determined by the clock rate adjustment apparatus may be adjusted dynamically in response to a required minimum clock rate and a variable data rate.

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Taipei, Taiwan

Bing-Yu Hsieh