Taiwan Semiconductor Manufacturing Comp. Ltd.

Doordash, Inc.

Bing Wang

Kuoyuan (Peter) Hsu

Derek C Tao

Kuoyuan Hsu

Young Suk Kim

Annie-Li-Keow Lum

Yukit Tang

Jacklyn Chang

Kai Fan

Subramani Kengeri

Jeff Ning Han

Rohan Balraj Chopra

Sungchieh Lin

William Preston Parry

Allen Fan

Ming-Chieh Huang

Sung-Chieh Lin

Young Seog Kim

Ming Chieh Huang

Described are systems and processes for generating dynamic estimated time of arrival predictive updates for delivery of perishable goods. In one aspect a system is configured for generating dynamic estimated time of arrival (ETA) predictive updates between a series of successive events for real-time delivery of orders. For each order, a plurality of delivery events and corresponding timestamps are received from devices operated by customers, restaurants, and couriers. Based on the timestamps, the system generates a plurality of ETA time predictions for one or more of the delivery events with trained predictive models that use weighted factors including historical restaurant data and historical courier performance. As additional timestamps are received for a delivery event, the trained predictive models dynamically update the ETA time predictions for successive events. The predictive models may be continuously trained by updating the weighted factors based on the received timestamps.

System for dynamic estimated time of arrival predictive updates

The present disclosure describes a power supply switch that includes a voltage generator, a switch circuit, and a confirmation circuit. The voltage generator is configured to compare a first power supply voltage to a second power supply voltage and to output the first power supply voltage or the second power supply voltage as a bulk voltage (V). The switch circuit includes one or more transistors and is configured to (i) bias bulk terminals of the one or more transistors with the Vand (ii) output either the first power supply voltage or the second power supply voltage as a voltage output signal. The confirmation circuit is configured to output a confirmation signal that indicates whether the voltage output signal transitioned from the first power supply voltage to the second power supply voltage.

Switchable power supply

In various embodiments, a circuit includes a first switch coupled to a voltage source and a bit-line (BL). The first switch is configured to couple the BL to the voltage source to charge the BL in response to a charge control signal. A second switch is coupled to the voltage source and a complimentary bit-line (BLB) and is configured to couple the BLB to the voltage source to charge the BLB in response to the charge control signal. A control circuit is electrically coupled to each of the first switch and the second switch. The control circuit is configured to generate the charge control signal. The charge control signal is configured to control the first switch and the second switch to selectively couple the BL and the BLB to the voltage source to charge the BL and the BLB from an initial voltage to a first predetermined voltage during a first discrete charging period and from the first voltage to a second predetermined voltage during a second discrete charging period.

Memory cell having a reduced peak wake-up current

A circuit includes a first latch for generating a first latched signal; and a first comparator for comparing the first latched signal and a write address, and generating a first comparator signal. The circuit includes a first logic circuit for receiving the first comparator signal and a fourth latched signal, and generating a first logic circuit output signal; and a second latch for receiving the first logic circuit output signal and generating a second latched signal. The circuit includes a third latch for generating a third latched signal; and a second comparator for comparing the third latched signal and a read address, and generating a second comparator signal. The circuit includes a second logic circuit for receiving the second comparator signal and the second latched signal, and generating a second logic circuit signal; and a fourth latch for receiving the second logic circuit signal and generating the fourth latched signal.

Circuit, method of using the circuit and memory macro including the circuit

An interface circuit is provided. A NMOS transistor is coupled between a first bit line and a ground. A logic gate is coupled between a gate of the NMOS transistor and a second bit line. A keeper controls a voltage level of the second bit line according to a reference voltage. A tracking circuit includes a plurality of reference bit cells and a pull-up device coupled to a reference bit line. Each reference bit cell is coupled to a read word line. When a bit cell coupled to the second bit line is accessed by a specific read word line, the reference bit cell coupled to the specific read word line drains a current from the pull-up device. The tracking circuit provides the reference voltage according to the current.

Memory and interface circuit for bit line of memory

A circuit includes a first power node that receives a first operational voltage having a first operational voltage level and a second power node that receives a second operational voltage having a second operational voltage level different from the first operational voltage level. A memory cell is coupled with the first power node, the memory cell configured to store a logic value, and a tracking cell is coupled with the second power node, the tracking cell configured to generate a signal having a timing responsive to the second operational voltage level. The circuit is configured to read the logic value of the memory cell based on the signal.

Tracking cell and method

A circuit has an operational voltage supply node that carries an operational voltage having an operational voltage value, a reference voltage supply node that carries a reference voltage having a reference voltage value, and a sub-circuit and switching circuit between the operational voltage supply node and the reference voltage supply node. The switching circuit is in series with the sub-circuit and controls a current through the sub-circuit based on a difference between the operational voltage value and a nominal operational voltage value.

Switching circuit for controlling current responsive to supply voltage values

A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal.

Tracking mechanism for writing to a memory cell

A circuit comprises a first transistor, a capacitive component, a second transistor, and a data line. The first transistor has a threshold voltage value. A first terminal of the first transistor is coupled with a first terminal of the capacitive component and a second terminal of the second transistor. A second terminal of the first transistor is configured to receive a second-terminal voltage value. A third terminal of the first transistor is configured to receive a third-terminal voltage value. A first terminal of the second transistor is coupled with the data line. A third terminal of the second transistor is configured to receive a second-transistor control signal. The first transistor is configured to be on and off to maintain the data line at a data line voltage value.

Writing data to a memory cell

A memory array includes an array of memory cells. The memory array further includes at least two read tracking cells in a read tracking column. The memory array further includes a read tracking circuit coupled to the at least two read tracking cells, wherein the read tracking circuit is configured to generate a global tracking result signal based on outputs from the at least two read tracking cells. The memory array further includes memory control circuitry, wherein the memory control circuitry is configured to reset a memory clock based on the global tracking result signal.

Memory array and method of operating the same

A circuit comprises a driver, a first capacitive device, and a second capacitive device. The driver has an input node, an output node, and a driver supply voltage node. The first capacitive device has a first terminal and a second terminal. The second capacitive device has a first terminal and a second terminal. The first terminal of the first capacitive device is configured to receive a first signal. The second terminal of the first capacitive device is coupled with the driver supply voltage node. The output of the driver is coupled with a first end of the second capacitive device.

Boosting voltage level

A circuit includes a first data line, a first plurality of memory cells coupled with the first data line, and a data transfer circuit coupled with the first data line. The data transfer circuit includes an output logic gate. The data transfer circuit is configured to, in a first operation mode in which the first plurality of memory cells is in a standby mode, set an output node of the output logic gate to be free from electrically coupled with a reference voltage and a supply voltage through the output logic gate. The data transfer circuit is configured to, in a second operation mode in which a memory cell of the first plurality of memory cells is selected to be read, set the output node of the output logic gate to be either electrically coupled with the reference voltage or with the supply voltage through the output logic gate.

Data circuit

A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line.

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Palo Alto, CA, United States of America

Bing Wang