Taiwan Semiconductor Manufacturing Comp. Ltd.

Bing-Hung Chen

Teng-Chun Tsai

Li-Ting Wang

Cheng-Tung Lin

Huan-Just Lin

Chih-Tang Peng

De-Fang Chen

Tze-Liang Lee

Hui-Cheng Chang

Yung-Cheng Lu

Ming-Hsing Tsai

Chien-Hsun Wang

Huang-Yi Huang

Hao-Ming Lien

Keith Kuang-Kuo Koai

Ru-Chien Chiu

Syun-Ming Jang Jang

Jyu-Horng Shieh

Sheng-Liang Pan

Shu-Huei Suen

Chia-Yang Hung

Jack Kuo-Ping Kuo

Chii-Horng Li

Ming-Ching Chang

Pang-Yen Tsai

Jr-Hung Li

Yih-Ann Lin

Wei-Jung Lin

Chih-Chang Hung

Hong-Mao Lee

Chi-Yuan Chen

Chia-Han Lai

Chieh-Ning Feng

Jhi-Cherng Lu

Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

DC bias in plasma process

In a method, an aluminum body is chemically treated with at least one of an alkaline solution and an acid solution. Anode-oxidization is performed on the chemically treated aluminum body to form an aluminum oxide layer. The aluminum oxide layer is treated with hot water at a temperature more than 75&#xb0; C. or steam. The aluminum oxide layer after being treated with hot water or steam includes plural columnar grains, and an average width of the columnar grains is in a range from 10 nm to 100 nm.

Aluminum apparatus with aluminum oxide layer and method for forming the same

According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

Method of forming isolation layer

A method includes forming a gate dielectric layer, forming a metal gate strip over a bottom portion of the gate dielectric layer, and performing a first etching process on the metal gate strip to remove a portion of the metal gate strip. The first etching process is performed anisotropically. After the first etching process, a second etching process is performed on the metal gate strip to remove a residue portion of the metal gate strip. The second etching process includes an isotropic etching process. A dielectric material is filled into a recess left by the etched portion and the etched residue portion of the metal gate strip.

Residue removal in metal gate cutting process

In a method, an aluminum body is chemically treated with at least one of an alkaline solution and an acid solution. Anode-oxidization is performed on the chemically treated aluminum body to form an aluminum oxide layer. The aluminum oxide layer is treated with hot water at a temperature more than 75 &#xb0; C. or steam. The aluminum oxide layer after being treated with hot water or steam includes plural columnar grains, and an average width of the columnar grains is in a range from 10 nm to 100 nm.

According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.

Vertical structure having an etch stop over portion of the source

Vertical structure and method of forming semiconductor device

A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer.

Method of temperature determination for deposition reactors

Systems and methods are provided for reducing a contact resistivity associated with a semiconductor device structure. A substrate including a semiconductor region is provided. One or more dielectric layers are formed on the semiconductor region, the one or more dielectric layers including an element. A gaseous material is applied on the one or more dielectric layers to change a concentration of the element in the one or more dielectric layers. A contact layer is formed on the one or more dielectric layers to generate a semiconductor device structure. The semiconductor device structure includes the contact layer, the one or more dielectric layers, and the semiconductor region. A contact resistivity associated with the semiconductor device structure is reduced by changing the concentration of the element in the one or more dielectric layers.

Systems and methods for reducing contact resistivity of semiconductor devices

A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.

Semiconductor device and method of manufacture

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Taipei, Taiwan

Bing-Hung Chen