United Microelectronics Corp.

Bing-Chang Wu

Kun-Chih Wang

Shiao-Shien Chen

Mei-Ling Chao

Chien-Li Kuo

Tung-Po Chen

Hong-Tsz Pan

Chen-Hui Chung

Jui-Meng Jao

Cheng-Hui Chung

A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.

Semiconductor chip capable of implementing wire bonding over active circuits

A reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. A metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding, when the thickness of said stress-buffering dielectric layer is greater than 2000 angstroms, the damascened metal frame may be omitted. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame.

A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure, a metal-metal capacitor formed by at least a pair of metal electrodes on the same plane underneath the bonding pad structure, at least an interconnection metal layer, at least a via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

A semiconductor structure is provided. The semiconductor structure is disposed on the scribe line of a wafer and is around the chip area of the wafer. The semiconductor structure includes a plurality of dielectric layers sequentially disposed on the scribe line and a plurality of metal patterns disposed in each dielectric layer. The metal patterns disposed in each dielectric layer extend to the next underlying dielectric layer.

Semiconductor structure and fabricating method thereof

A method of fabricating high resistivity thin film resistors. An isolation region is formed on a substrate to isolate the active regions. A polysilicon layer is formed above the substrate. A diffusion barrier layer is formed above the polysilicon layer. Lightly doped ions are implanted in the polysilicon layer. The substrate is annealed at a high temperature. The diffusion barrier layer and the polysilicon layer are patterned to form a high-resistive thin film resistor. Spacers are formed on the sidewalls of the high-resistive thin film resistor.

Method for fabricating a thin film resistor

A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

A processing method for fabricating silicide is provided. First of all, a semiconductor structure having a semiconductor surface and an insulation surface is provided. Next, an epitaxial layer on the semiconductor surface is formed. And, the semiconductor structure is treated. The treat step is that the removal rate of the insulation surface is faster than the removal rate of the epitaxial layer. Then, a metal layer on the epitaxial layer is formed. Finally, heating the epitaxial layer forms silicide. The treatment step prevents the insulation surface from the formation of the silicide so as to reduce the degradation of device characteristics.

Method for fabricating silicide by heating an epitaxial layer and a metal layer formed thereon

An integrated circuit including a reinforced bonding pad structure is disclosed. The reinforced bonding pad structure includes a bondable metal layer defined on a stress-buffering dielectric layer, and an intermediate metal layer damascened in a first inter-metal dielectric (IMD) layer disposed under the stress-buffering dielectric layer. The intermediate metal layer is situated directly under the bondable metal layer and is electrically connected to the bondable metal layer with a plurality of via plugs integrated with the bondable metal layer. At least one metal frame is damascened in a second IMD layer under the first IMD layer. The metal frame is situated directly under the intermediate metal layer for counteracting mechanical stress exerted on the bondable metal layer during bonding. An active circuit portion including active circuit components of the integrated circuit is situated directly under the metal frame of the reinforced bonding pad structure.

This invention relates to a method for decreasing the resistivity of the gate and leaky junction of the source/drain, more particularly, to the method for forming a metal silicide layer at the gate region and the source/drain region by using two times in depositing metal layer. This condition will form a thicker metal silicide layer at the gate region to decrease the resistivity of the gate and will form a thinner metal silicide layer at the source/drain region to decrease defects in leaky junction at the source/drain region. At first, a semiconductor substrate is provided and a MOS is formed on the substrate and a shallow trench isolation is formed in the substrate. The MOS comprises a gate region, a source region, a drain region, and a spacer which is formed on the sidewall of the gate. The first metal layer is formed over the MOS and a oxide layer is formed over the first metal layer. Partial oxide layer is etched to show the first metal layer which is formed on the gate. The first metal layer which is on the gate is removed. The remained oxide is removed. The second metal layer is formed on the first metal layer. Then two times rapid thermal process are passed through and the salicide process is finished.

Method for decreasing the resistivity of the gate and the leaky junction of the source/drain

A semiconductor wafer has a dielectric layer. A bottom plate recess is first formed in the dielectric layer, and a metal bottom plate is formed in the bottom plate recess. An insulation layer is formed on the metal bottom plate, and a via hole is formed in the insulation layer. A first metal layer is then formed on the insulation layer that fills the via hole so as to form a via plug. Finally, a metal upper plate is formed on the insulation layer, and a metal wire is formed on top of the via plug.

Method for forming a metal capacitor

A method for improving the fabrication of a transistor barrier layer that utilizes an ion bombardment treatment after the formation of the titanium nitride layer for reducing contact resistance and preventing tungsten plug stringer generation. The method comprises the step of patterning a transistor to form vias, and then depositing a titanium/titanium nitride layer over the transistor surface using a collimator sputtering method. Next, an ion bombardment treatment is carried out, and then a rapid thermal processing operation is performed. Finally, tungsten is deposited to fill the vias follow by a planarization. This invention is able to lower contact resistance because titanium in the titanium layer will not react with gaseous ammonia or nitrogen in the reacting chamber to form a high resistance titanium nitride layer during rapid thermal processing operation. In the meantime, no short-circuiting stringers leading from the tungsten plug to the titanium nitride layer below are formed because no cracks are formed in a titanium nitride layer that has been subjected to a stress reducing ion bombardment treatment.

Method of manufacturing transistor barrier layer

A two-step silicidation process for fabricating a semiconductor device is disclosed. The method includes the following steps. Firstly, two trench isolation regions are formed in a semiconductor substrate. A gate oxide layer and a polysilicon layer and a barrier layer are formed. Patterning is carried out to etch portions of the barrier layer. The areas between the trench isolation regions and the gate region are respectively used as a source area and a drain area. First ions are implanted into the substrate. A dielectric layer is blanket formed and the dielectric layer is etched back to form dielectric spacer. The second ions are implanted into the substrate. The first silicide regions respectively are formed in the source area and the drain area. A poly-metal dielectric (PMD) layer is formed and is etched back. Finally, the second silicide region is formed on and in the polysilicon layer.

Two-step silicidation process for fabricating a semiconductor device

The present invention is a method for preventing the peeling phenomena of the Tungsten metal in the integrated circuit after the metal-etching process. A semiconductor's substrate is provided. An integrated circuit is manufactured in the substrate. An intermetal-dielectric layer is formed on the substrate and it has the contacting holes and the verniers. A barrier layer is also formed on the intermetal-dielectric layer. A tungsten-metal layer is then deposited on the barrier layer. The barrier layer and the tungsten-metal layer are etched back to form the plugs of the contacting holes, the spacers of the vernier and the metal stoppers, which cover the edges of the verniers. Thus, the metal stoppers have a good adhesion with the barrier layer and the peeling of the tungsten spacer is prevented.

Method for preventing the peeling of the tungsten metal after the metal-etching process

A method for improving the planarization of a dielectric layer in the fabrication of metallic interconnects wherein a rapid thermal processing operation is used in order to consolidate exposed surfaces of a dielectric layer after local planarization of the dielectric layer. This method avoids damage to the dielectric layer caused during a pre-metal etching operation, and consequently, prevents residual tungsten from becoming lodged in fissures during subsequent tungsten deposition to produce stringers which may cause short circuiting on coming in contact with metal wiring.

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Hsin-Chu Hsien, Taiwan

Bing-Chang Wu