Intel Corporation

Bindi A Prasad

Peter D MacWilliams

William S Wu

Dilip K Sampath

Muthurajan Jayakumar

Stephen S Pawlowski

Gurbir Singh

Dan Wheeler Patterson

Sunny C Huang

Phil G Lee

Leonard J Schultz

Manoji Khare

Steve Hunt

A method and apparatus for transferring data between bus agents in a computer system. The present invention includes transmitting a control signal, from a first agent to a second agent, via a first transfer protocol; and, transmitting data corresponding to the control signal, from the first agent to the second agent, via a second transfer protocol. In one embodiment, the control signals are transmitted from the first agent to the second agent via a synchronous transmission with respect to a bus clock; and, the data is transmitted via an asynchronous transmission with respect to the bus clock, which has a data width greater than the synchronous transmission. In addition, in one embodiment of the present invention, the synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.

Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system

Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system

A source synchronous interface between a master device and slave device is described. A master device having a plurality of deskew latches is coupled to a slave device via a bus. The master device communicates commands and first timing information to the slave device via the bus. In response, the slave device communicates data and second timing information to the master device via the bus. When data is communicated from the slave device to the master device, the data is stored in one of the plurality of deskew latches until accessed by the master device. The plurality of deskew latches ensure that the master device will always read valid data for the full range of skew of the first and second timing information.

Source synchronous interface between master and slave using a deskew latch

A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A second level cache memory is also coupled to the cache bus. The cache control circuit controls the second level cache by issuing commands that are executed by the second level cache.

Processor-cache protocol using simple commands to implement a range of cache configurations

A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.

Method and apparatus for performing bus operations in a computer system

In a microprocessor system having a bus clock running at a bus clock rate, a method for reducing an idle interval between a first data transfer and a second data transfer, the method comprising the steps of:

Mechanism for data strobe pre-driving during master changeover on a

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Los Altos, CA, United States of America

Bindi A Prasad