Nanjing University of Posts and Telecommunicatins

Nantong Institute of Nanjing University of Posts and Telecommunications Co.,ltd.

Positec Power Tools (suzhou) Co., Ltd.

Binbin Xu

Yufeng Guo

Zhikuang Cai

Zixuan Wang

Jiafei Yao

Henglu Wang

Guopeng Zhou

Jian Song

Zushuai Xie

Shisong Zhang

Hongfeng Zhong

Xiaoli Pang

Jian Xiao

Jingtao Xu

Hongbing Wu

Guojun Chen

Zhen Zhang

Lu Liu

Haijun Shen

Yunbo Wang

Haiyan Sun

Dapeng Yan

Luping Zhang

Xianghua Meng

Xiaoting Liu

A universal test chiplet for testing a plurality of chiplets to be tested is provided. The universal test chiplet includes a chiplet test control circuit module, a test data distribution circuit module, a memory test configuration circuit module, and a chiplet test interface circuit module. The chiplet test control circuit module is configured to provide test data and configure test modes for the chiplets to be tested. The test data distribution circuit module is configured to distribute the test data required by each of the chiplets to be tested from a test data bus. The memory test configuration circuit module is configured to provide test circuits for memories of the chiplets to be tested and automatically generate a test vector. The chiplet test interface circuit module is configured to transmit the test data to the chiplets to be tested in any direction through chiplet test interfaces.

Universal test chiplet

A circuit for post-binding testing of a 2.5D chiplet includes an interposer-dedicated TAP controller, an interposer test interface circuit and a chiplet test output control circuit. A chiplet test configuration register and its corresponding instructions are newly added for the interposer-dedicated TAP controller. The interposer test interface circuit uses an output control signal of the chiplet test configuration register to select the opening or closing of a test signal channel between an interposer and a chiplet. The chiplet test output control circuit uses the chiplet test configuration register to output a control signal for control of a test data output of the chiplet on the interposer.

Circuit and method for post-binding testing of 2.5D chiplet

Disclosed is a serial test circuit for controllable Chiplets, which belongs to the technical field of test or measurement of semiconductor devices during manufacturing or processing. The test circuit includes a master control test module, a slave control test module, a clock controlling module and an outputting module. The master control test module is composed of a test access port module, a segment insertion bit module and a test data register module. The test controlling signal is generated by the master control test module, and the test inputting signals of the slave Chiplets are respectively controlled by the slave control test module after receiving the test controlling signal. At the same time, the test controlling signal is inputted to the clock controlling module to obtain the clock signals of the slave Chiplets. The output signal of the test outputting module is determined by the test controlling signal.

Serial test circuit for controllable Chiplets

The present disclosure relates to the field of design for testability of super-large-scale integrated circuits, and discloses a flexible configurable module (FCM) based chiplet test circuit. The core structure of the circuit is located at an interposer. The test circuit includes FCMs, a control signal configuration module and a test state control module, where the FCM adopts a two-way skew-symmetric structure to implement data transmission in the horizontal direction and the vertical direction; the control signal configuration module is connected to control signals of all the FCMs, so as to control the data transmission directions as well as switch on and switch off states of all the FCMs; and the test state control module controls the shift and update operations of data inside the FCMs and the control signal configuration module.

FCM based chiplet test circuit

A dust bin and a vacuum cleaner combination provided with the dust bin are provided. The dust bin includes a dust chamber, a dust inlet detachably connected to a dust suction apparatus, and a sealing structure for implementing the sealing between the dust suction apparatus and the dust bin. The dust suction apparatus has a dust outlet joined to the dust inlet. The vacuum cleaner combination includes a dust suction apparatus and a dust bin detachably connected to the dust suction apparatus. The dust suction apparatus has a housing and a dust cup assembly connected to the housing. The dust cup assembly includes a cup body and a filter apparatus disposed in the cup body. Compared with the prior art, in the present invention, a detachable multi-purpose dust bin with a simple structure is disposed, so that the dust collection chamber of the vacuum cleaner is flexibly increased.

Dust bin, vacuum cleaner combination and stick vacuum cleaner

Growing community of inventors

Jiangsu, China

Binbin Xu