Micron Technology Incorporated

Binbin Huo

Vincenzo Reina

Rainer Frank Bonitz

The disclosure relates to improvements in command execution in semiconductor devices. In some aspects, the techniques described herein relate to an apparatus including: a storage array; and a processor configured to: receive a command from a host processor, start to profile the command by initializing a counter at a first time, issue the command to the storage array, receive a response to the command, end profiling of the command at a second time, and update a command timing for a type of the command.

Monitoring and exporting command execution times in a semiconductor device

Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

Advanced power off notification for managed memory

Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.

Parameter table protection for a memory system

Methods, systems, and devices for techniques to retire unreliable blocks are described. A memory system may receive a request for information about a quantity of erase operations performed on a block of the memory system. Based on the request, the memory system may determine the quantity of erase operations performed on the block and transmit an indication of the quantity of erase operations performed on the block.

Techniques to retire unreliable blocks

Various embodiments enable sending a notification to a host system based on an address mapping entry miss (or mismatch) on a memory sub-system, which can facilitate an update of one or more address mapping entries stored on the host system.

Host system notification based on entry miss

Methods, systems, and devices for host side memory address management are described. In some examples, a host system may identify a read request that includes a logical address of a block of a memory device. The read request may be associated with a descriptor indicating a page of a cache of the host system. The host system may determine to assign a descriptor to a page of the cache, and may recycle one or more pages of the cache. In some examples, the host system may determine whether the page indicated by the descriptor includes a mapping between the logical address and a physical address of the memory device, and may issue a read command to the memory device based on the page including the mapping.

Host side memory address management

A computing system can comprise a processing resource and a memory device coupled together via a first transmission link. The processing resource can be configured to test the first transmission link in response to the memory device failing to execute a command by sending the command to the memory device again for retry and monitoring the first transmission link for signals that indicate whether the command was executed by the memory device.

Transmission link testing

A method and system for retransmitting messages in a memory subsystem are described. A message is transmitted to a host system. A response message is expected to be received from the host system in response to the message. A determination that the response message was not received prior to detecting an indication of a processing of a number of commands from the host system is performed. The message is retransmitted to the host system in response to the determination.

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Sauerlach, Germany

Binbin Huo