Texas Instruments Corporation

Burr-brown Corporation

Binan Wang

Mark Allan Shill

Timothy V Kalthoff

Miaochen Wu

Paul Stulik

James Lee Todsen

Ka Yin Leung

Abdullah Yilmaz

Kevin A Huckins

Binling Zhou

Robert M Schreiber

Souichirou Ishizuka

Haibing Zhang

A current mirror circuit includes a current output terminal, a first transistor, a second transistor, and a digital-to-analog converter (DAC). The first transistor includes a first terminal coupled to a power rail, a second terminal coupled to a current source, and a third terminal coupled to the current source. The second transistor includes a first terminal coupled to the power rail, a second terminal coupled to the second terminal of the first transistor, and a third terminal coupled to the current output terminal. The DAC includes an output terminal coupled to the second transistor.

Current mirror circuit

In some examples, a system includes an integrated circuit comprising a transistor, a first amplifier coupled to the transistor, a second amplifier having an output and coupled to the transistor and the first amplifier, and an R-2R resistor ladder having multiple rungs. Each rung is switchably coupled to a terminal of the transistor and to the output of the second amplifier. The R-2R resistor ladder includes a resistor coupled to either the transistor or the output of the second amplifier.

R-2R resistor ladder trim circuits

A delta sigma modulator includes two adders, an integrator stage, a reconfigurable local resonator, an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC). A first adder receives an analog input signal at an additive input, and the integrator stage receives an output from the first adder and generates an integrated signal. The reconfigurable local resonator receives the integrated signal and generates a resonator output signal. A second adder receives the resonator output signal, the integrated signal, and the input signal. The ADC receives an output from the second adder and generates a digital output signal which can be provided to other circuits. The DAC receives the digital output signal, and generates and provides a feedback signal to a subtractive input of the first adder. The reconfigurable local resonator acts as a resonator, but reconfigures to act as a low pass filter in response to overload conditions.

Overload recovery method in sigma delta modulators

A voltage regulation system provides a relatively stable voltage source without introducing the typical costs of a ground buffer. The disclosed voltage regulation system includes a voltage regulator that is operative to detect a change of the load current and regulate a current bypass mechanism to stabilize a total supply current. For example, the voltage regulator includes a current sensor and a current compensation circuit. The current sensor is configure to generate a current compensation signal based on the load current change, whereas the current compensation circuit is configured to adjust a bypass current in response to the current compensation signal. As a result, the bypass current dynamically compensates the load current change such that the ground voltage of a variable load becomes relatively stable over a range of load currents.

Voltage regulator with load compensation

A power on reset (POR) circuit is provided. For the POR circuit, a PMOS transistor is coupled to a first voltage rail at its source. A drive circuit is coupled to the drain of the PMOS transistor and is configured to output a POR signal. A voltage divider is coupled between the drain of the PMOS transistor and the second voltage rail. A switch network is provided as well, which has first and second switches. The first switch is coupled between the gate of the PMOS transistor and the voltage divider, and the second switch is coupled between the gate of the PMOS transistor and the voltage divider. A controller is also coupled to control the first and second switches, wherein the first and second switches are complementary driven.

Power on reset apparatus

A cascaded delta-sigma modulator includes a first stage delta-sigma modulator (A) having first adder () followed by first () and second () integrators, a second adder (), and a quantizer () the output of which is fed back to the first adder by an A/D (). A gain circuit () is also connected between the first integrator and the second adder. The quantizer output is coupled by interstage circuitry to a second stage converter (B) having a transfer function represented by the expression OUT(z)=zIN(z)+G(z)E2(z). An error cancellation circuit () includes inputs coupled to the output of the quantizer and an output of the second stage converter so as to provide a flat transfer function of the cascaded first stage delta-sigma modulator and second stage converter and the error cancellation circuit, despite non-flatness in a transfer function of the first stage delta-sigma modulator.

Feed-forward circuitry and corresponding error cancellation circuit for cascaded delta-sigma modulator

A synchronous DC-to-DC converter includes an inductor coupled to receive an input voltage, a first transistor having a source coupled to a first reference voltage and a drain coupled to the inductor, and a second transistor having a source coupled to an output conductor to produce an output voltage and a drain coupled to the inductor. A feedback signal representative of a value of the output voltage is generated, and a switch control signal is produced in response to the input voltage and a second reference voltage. The second transistor is turned off in response to the switch control signal each time the inductor current has decayed to zero to prevent reverse current flow through the inductor. A regulating signal indicates whether or not the feedback voltage exceeds the second reference voltage, to regulate the output voltage in a pulse-frequency modulation mode.

Predictive duty ratio generating circuit and method for synchronous boost converters operating in PFM mode

A voltage monitor circuit for biasing a well region of a CMOS circuit includes a self-biased comparator which compares first (INP) and second (INN) input signals. The comparator includes first (MN) and second (MN) N-channel transistors with grounded sources, a drain of the first N-channel transistor and a gate of the second N-channel transistor being coupled to a first output (OUTN), and a drain of the second N-channel transistor and a gate of the first N-channel transistor being coupled to a second output (OUTP). First (MP) and second (MP) P-channel transistors are operated to couple the second or first input signal to the second or first output, respectively, by controlling the gate-to-source voltage of the first or second P-channel transistor according to the polarity of a voltage difference between the first and second input signals.

Self-biased comparator with hysteresis control for power supply monitoring and method

A voltage-to-current conversion circuit includes an error amplifier (A) which amplifies a voltage difference between the drains of the first () and second () transistors of a first current mirror, wherein drain current of the first transistor is proportional to an input voltage (Vin). The output of the error amplifier is connected to the gates of the first and second transistors. A compensation capacitor is coupled between the gate and drain of the first transistor. The drain current of the second transistor flows through a cascode transistor () to an input of a second current mirror, an output transistor () of which provides a current (Ibias) which is proportional to the input voltage (Vin) as a bias current for the error amplifier, to provide stable operation.

Precision current mirror and method for voltage to current conversion in low voltage applications

A phase detector in a delay locked loop circuit operates to determine the status of propagation of a first pulse of a reference clock signal (CKref) through a delay line (). A first control signal (DOWN) is produced a in response to represent a first time at which the first pulse has progressed entirely through the delay line () and a later second time at which a next second pulse of the reference clock signal (CKref) arrives at a first input of the phase detector (A). The delay of the delay line () is reduced in response to the first control signal (DOWN). A second control signal (UP) is produced in response to the status to represent a third time at which the second pulse of the reference clock signal (CKref) arrives at the first input of the phase detector (A) and a later fourth time at which the first pulse of the reference clock signal (CKref) has progressed to the end of the delay line () and is used to increase the delay of the delay line ().

False-lock-free delay locked loop circuit and method

Bias current in output transistors of a class AB output stage is controlled by providing equal amplification to both an output of an input stage ( ) of an amplifier and an output ( ) of a class AB control circuit ( ). A split input transistor circuit structure for a first side of the differential input stage ( ) includes first ( ) and second ( ) input transistors with gates coupled to a first input (Vin&plus;). A third input transistor ( ) of the input stage has a gate coupled to a second input (Vin&minus;). A split folded common gate cascode circuit includes first ( ) and second ( ) cascode transistors having their drains coupled to gates of the output transistors, respectively, and a third cascode transistor has a source coupled to a drain of the third input transistor. The bias current is sensed and compared with a reference current to produce an error signal that is amplified to produce a differential error current a signal which is introduced applied to sources of the first and second cascode transistors.

Class AB operational amplifier with split folded-cascode structure and method

A Miller de-compensation technique and circuit is provided for a differential input, differential output (DIDO) amplifier that facilitates increased differential mode bandwidth while maintaining common-mode and differential mode stability. An exemplary differential input, differential output (DIDO) amplifier comprises a pair of op amps having a compensation capacitance circuit. The compensation capacitance circuit is configured to distinguish between differential mode signals and common mode signals, and to reduce the effects of compensation capacitance during differential mode operation, but allow the effects of compensation capacitance to remain present during common mode operation. As a result, the amount of compensation capacitance can be configured such that common mode stability can be maintained without reducing differential mode bandwidth. The DIDO amplifier can be configured as a programmable gain amplifier or a fixed gain amplifier. In addition, the compensation capacitance circuit can be configured with a switched-capacitor network for selectively cross-coupling compensation capacitors for de-compensation.

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Tucson, AZ, United States of America

Binan Wang