Agora Lab, Inc.

Micron Technology Incorporated

Exxonmobil Chemical Patents Inc.

Palo Alto Networks, Inc.

Alcatel Lucent

National Cheng-kung University

Inventec Appliances Corporation

Tongji University

Baoshan Iron & Steel Co., Ltd.

Shanghai Micro Electronics Equipment (group) Co., Ltd.

Bin Zhao

Liang Li

Wei Zhang

Xu Zhang

Qi Zhang

Jiangxia Liu

Jie Yang

Xing Wang

Shan Jin

Liu Yang

Xiaolai Zhu

Yong Liang Liu

Robert J Wittenbrink

Sheng Zhong

Deping He

Aspy Keki Mehta

Jie Huang

Jie Hui Xu

Xinghui Duan

Na Li

George James Pehlert

Guobao Li

Yongjie Yang

Kanyi Shen

Xingxing Wang

Achiel J M Van Loon

Yi Ping Ni

Huabing Zhang

Charles R Harris

Zhuochao Hu

Shuangjie Chu

Qi Xu

Peili Zhang

Shanshan Zhang

Jonathan Li

Lingyun Wang

Yujian Wang

Yongming Gai

Luis A Sotomayor

Yezhong Sun

Zhijun Huo

Chen Wan

Hui Fu

Yurun Sun

Yi Peng

Jianxiong Huang

William A Ramsey

Yong Liu

Galen C Richeson

Chih-Chin Ko

Qingyun Qian

Haiyin Hua

Zhaohui Jiang

Gregory E Keys

Qingqing Lun

Weihua Huang

Zhiji Zhang

Yun-Che Wang

Hai-Jie Ge

Yun-Feng He

Hua-Yin Zhang

Yuangen Yu

Abigail I Agentis

Li Zu Wang

Peite Bao

Zhen Yu Gong

Ying Ying Sun

Methods, systems, and devices for memory write performance techniques are described. A memory system may receive a sequence of commands, for example from a host system. Based on a relationship between logical block addresses of the sequence of commands, the memory system may delay performing a memory management operation (e.g., a garbage collection procedure, a power operation, a cache synchronization operation, a data relocation operation, or the like) for a duration. For example, the memory system may determine whether a quantity of write commands in the sequence that include non-consecutive logical block addresses exceeds a threshold. In some cases, the memory system may perform one or more commands in the sequence during the duration. Subsequently (e.g., at the end of the duration), the memory system may perform the memory management operation.

Memory write performance techniques

Methods, systems, and devices for performance benchmark for host performance booster are described. The memory system may receive a plurality of read commands from a host system. The memory system may detect a pattern of random physical addresses as part of the plurality of read commands and increase an amount of space in a cache of the memory system based on the detected pattern. In some cases, the amount of space may be used for mapping between logical block addresses and physical addresses. The memory system may determine, for a different plurality of read commands, whether a rate of cache hits for a portion of the mapping satisfies a threshold. In some cases, the memory system may determine whether to activate a host performance booster mode based on determining whether the rate of cache hits satisfies the threshold.

Performance benchmark for host performance booster

Methods, systems, and devices for mitigating memory die misalignment are described. A memory system may receive a command to write data to a memory device including a memory die. The memory system may determine whether the data indicated by the command (e.g., a first set of data) satisfies a threshold size. If the first set of data satisfies the threshold size, the memory system may determine whether data currently in a write buffer aligns with a boundary of the memory die. For example, depending on the data currently in the buffer, adding the first set of data to the buffer may result in die misalignment for the first set of data. To mitigate die misalignment, the memory system may pad data (e.g., add dummy data) to the write buffer, such that the padding aligns the data with the die boundary.

Techniques to mitigate memory die misalignment

Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.

Dynamic memory management operation

Methods, systems, and devices for managing regions of a memory system are described. A memory system may include a non-volatile memory device and may receive a host performance booster (HPB) command (e.g., a read command) associated with one or more regions of the non-volatile memory device. The memory system may determine whether the region(s) associated with the HPB command are active. In instances where one or more of the associated regions are inactive, the memory system may activate the region(s) and deactivate one or more other regions based on a recency parameter (e.g., a timing parameter). The memory system may process the received HPB command based on the associated region(s) being active.

Managing regions of a memory system

Methods, systems, and devices for read operations for active regions of a memory device are described. A memory system that includes a non-volatile memory device may receive a command to enter a first power mode. Before entering the first power mode, the memory system may store an indication of the active regions of the non-volatile memory device that are active for use as part of a host performance booster (HPB) mode. The memory device may receive an HPB command while in the first power mode, and may subsequently enter (e.g., re-enter) the second power mode. In some examples, the HPB command may be processed based on its physical address being included in one of the active regions of the non-volatile memory device.

Read operations for active regions of a memory device

Devices and techniques for improving memory access operations of a memory device are provided. In an example, a method can include loading multiple LBA-to-physical address (L2P) regions of an L2P table from memory arrays of the memory device to a mapping cache in response to determining the LBA of the memory access command is not within the L2P region including of a mapping cache. When the memory access command is a sequential command, the multiple L2P regions loaded to the mapping cache can provide improved memory access performance.

Pre-load techniques for improved sequential memory access in a memory device

A client device requests a web page via a clientless VPN. In response to the request, web page content comprising at least one script element is received at the clientless VPN. The clientless VPN inserts a wrapper function around at least a portion of the script element, forming modified web content. The client device is provided with the modified web content.

Encoding-free JavaScript stringify for clientless VPN

Disclosed are compositions comprising at least one polyolefin, a hindered phenol, and a phenyl phosphite; wherein the overall concentration of the hindered phenol and phenyl phosphite is within a range from 10 ppm to 5000 ppm in the polyolefin, and wherein the amount of the hindered phenol is less than the phenyl phosphite. Also disclosed herein are compositions comprising at least one polypropylene, a neutralizer, a hindered phenol, and a phenyl phosphite; wherein the overall concentration of the hindered phenol and phenyl phosphite is within a range from 1000 ppm to 5000 ppm in the polyolefin, and wherein the amount of the hindered phenol is from 200 to 2000 ppm less than the phenyl phosphite.

Low odor and volatiles polyolefin compositions and methods of production

The present invention relates to systems and methods for network labeling in order to enhance real time data transfers. A network for a real time data transfer is identified and predictive models for network performance are compared against to determine if the network is suitable for the data transfer. If so, then the real time data transfer may be completed as expected. However, if the network is predicted to be unsuitable for transmission an alternate means for connection may be suggested. The alternate suggestion may include delaying the data transfer until the network is expected to be in better conditions, connecting to another access point in the network, or switching to another network entirely. During the data transfer, the quality of the network is monitored in order to update the predictive models for the network's quality. Identifiers for the network may be utilized to keep track of the networks. Network signal strength, signal pollution and time may also be tracked in order to identify patterns in the network's performance.

Systems and methods for optimization of transmission of real-time data via network labeling

A vacuumizing device includes a vacuum chamber, a bonding fixture and a vacuumizing system. The bonding fixture is disposed in the vacuum chamber and includes a substrate table provided with a plurality of grooves for retention of the substrate by suction. The vacuumizing system is disposed in communication with both the vacuum chamber and grooves. During vacuumizing by the vacuumizing system, a vacuum value in the grooves is smaller than or equal to a vacuum value in the vacuum chamber. In the vacuumizing device and methods, the vacuumizing system is used to vacuumize the grooves in the substrate table and the vacuum chamber so that the vacuum value in the grooves is always smaller than or equal to that in the vacuum chamber. As a result, the substrates are firmly retained on the substrate table without warping, thereby improving the quality of substrate bonding.

Vacuumizing device and vacuumizing method for bonding substrate

Encoding-free javascript stringify for clientless VPN

Disclosed are propylene-based articles which can provide desired glossy surface including an impact copolymer substrate and a propylene-based elastomer body part overmolding, and a method of making such articles.

Articles comprising polypropylene impact copolymers and methods of making the same

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Shanghai, China

Bin Zhao