Qualcomm Incorporated

Peking University

Globalfoundries Inc.

International Business Machines Corporation

Beijing Founder Electronics Co., Ltd.

Boe Technology Group Co., Ltd.

Ke.com (beijing)technology Co., Ltd.

Beijing Boe Display Technology Co., Ltd.

North China Electric Power University

General Electric Company

Lenovo (beijing) Limited

Yonsei University

Hefei Boe Optoelectronics Technology Co., Ltd.

Intermolecular, Inc.

Beijing Lenovo Software Ltd.

Bin Yang

Xia Li

Gengming Tao

Christian Lavoie

Zhen Zhang

Lixin Ge

Man Fai Ng

Haining S Yang

Ye Lu

Haifeng Li

Junjing Bao

Ahmet Serkan Ozcan

Pr Chidambaram

Periannan Chidambaram

Seung Hyuk Kang

Jun Yuan

Lidong Wang

Yun Yue

Marwan H Khater

Choh Fei Yeap

Zhongze Wang

John Jianhong Zhu

Kai Liu

Jihong Choi

Paul Michael Solomon

Stanley Seungchul Song

Ming Cai

Yuke Yang

Yilang Hu

Hao Liu

Wilfried Haensch

Emre Alptekin

Seong-Ook Jung

Michael John Hargrove

Li Ping Yang

Jeffrey Xu

Rohit Pal

Tianshu Bi

Xiaoyan Shao

Cung D Tran

Xiaonan Chen

Mark V Raymond

Giridhar Nallapati

Ke Jia

Yi Zhu

Jianguo Yao

Jinwei Zhu

Christine Qiqing Ouyang

P R Chidambaram

Younghwi Yang

Ghavam G Shahidi

Gang Wang

Tak H Ning

Jonghae Kim

Michael A Guillorn

Dipankar Pramanik

Kisik Choi

Daeik Daniel Kim

Francesco Carobolante

Yu Zhu

Stephen Mark Rossnagel

Chen Chen

Qi Guo

Viraj Yashawant Sardesai

Andy C Wei

Yanxiang Liu

Ravi Mahendra Todi

Olov B Karlsson

Jun Zhou

Lei Jia

John S Foster

Yu Lu

Xing Xing Shen

Jia Tian Zhong

Feng Chen

Amol Ramesh Joshi

Shurong Liang

Jimmy Jianan Kan

Kejia Wang

Da Yang

Qingqing Liang

Ruina Zhang

Shuang Hong Wang

Andrew John Kellock

Xiao Lu

Zhendong Hong

Zhihong Liu

Pankaj Deshmukh

Stefan Zollner

Usha Raghuram

Xiaoju Yu

Chock Hing Gan

Bo Bai

Zhihui Sun

Namin Kwon

Bei Li

Charlene Chen

Jingang Su

Samit Sengupta

Francis M Tambwe

A monolithic 3D complementary field-effect transistor (FET) (CFET) circuit includes a first CFET structure and a second CFET structure in a logic circuit within a device layer. A first interconnect layer disposed on the device layer provides first and second input contacts and an output contact of a logic circuit. Each CFET structure includes an upper FET having a first type (e.g., P-type or N-type) on a lower FET having a second type (e.g., N-type or P-type). The FETs in the monolithic 3D CFET circuit may be interconnected to form a two-input NOR circuit or a two-input NAND circuit. Vertical access interconnects (vias) may be formed within the device layer to interconnect the FETs externally and to each other. The FETs may be formed as bulk-type transistors or SOI transistors.

Monolithic three-dimensional (3D) complementary field effect transistor (CFET) circuits and method of manufacture

An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.

P-type field effect transistor (PFET) on a silicon germanium (Ge) buffer layer to increase Ge in the PFET source and drain to increase compression of the PFET channel and method of fabrication

A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area.

FinFET semiconductor device

Disclosed are examples of multiple bit magnetoresistive random access memory (MRAM) cells. A multiple bit MRAM cell may comprise a fixed layer, alternately stacked N tunnel barriers and N free layers, and a tunnel cap. N, which may represent number of bits of the MRAM cell, may be greater than or equal to two. Magnetic moment of the fixed layer may be fixed in one perpendicular direction. Magnetic moments of the free layers may be switchable from one to other perpendicular directions upon application of switch currents. The switch currents may be different for different layers. The magnetic moments of the free layers may be switched separately or otherwise independently of other free layers when the switch currents are applied separately.

One transistor one magnetic tunnel junction multiple bit magnetoresistive random access memory cell

Three-dimensional (3D) interconnect structures employing via layer conductive structures in via layers are disclosed. The via layer conductive structures in a signal path in an interconnect structure are disposed in respective via layers adjacent to metal lines in metal layers. The via layer conductive structures increase the conductive cross-sections of signal paths between devices in an integrated circuit (IC) or to/from an external contact. The via layer conductive structures provide one or both of supplementing the height dimensions of metal lines and electrically coupling metal lines in the same or different metal layers to increase the conductive cross-section of a signal path. The increased conductive cross-section reduces current-resistance (IR) drop of signals and increases signal speed. As metal track pitches are reduced in size, signal path resistance increases. The via layer conductive structures are provided to reduce or avoid an even greater increase in resistance in the signal paths.

Three-dimensional (3D) interconnect structures employing via layer conductive structures in via layers and related fabrication methods

Disclosed is apparatus including a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers separates each of the plurality of dielectric layers. A first spiral coil is arranged in a first plane perpendicular to the substrate, where the first spiral coil is formed of first portions of the plurality of conductive layers and a first set of vias of a plurality of vias, configured to connect the first portions of the plurality of conductive layers.

Three dimensional (3D) vertical spiral inductor and transformer

A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.

Mitigation of duty-cycle distortion

Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.

Static random-access memory (SRAM) compute in-memory integration

Certain aspects are directed to a static random access memory (SRAM) including an SRAM cell with a pass-gate (PG) transistor having increased threshold voltage to improve the read margin of the SRAM cell. The SRAM generally includes a first SRAM cell having a pull-down (PD) transistor and a PG transistor coupled to the PD transistor. In certain aspects, the SRAM includes a second SRAM cell, the second SRAM cell being adjacent to the first SRAM cell and having a PD transistor and a PG transistor coupled to the PD transistor of the second SRAM cell. The SRAM may also include a gate contact region coupled to a gate region of the PG transistor of the first SRAM cell, wherein at least a portion of the gate contact region is offset from a midpoint between the first SRAM cell and the second SRAM cell.

Fin field-effect transistor (FinFET) static random access memory (SRAM) having pass-gate transistors with offset gate contact regions

Disclosed are semiconductor devices including a double gate metal oxide semiconductor (MOS) transistor and methods for fabricating the same. The double gate MOS transistor includes a first back gate, a second back gate, and a first dielectric layer disposed on the first back gate and on the second back gate. An MX2 material layer is disposed on the first dielectric layer, a second dielectric layer disposed on the MX2 material layer, and a work function metal (WFM) is disposed on the second dielectric layer. A front gate is disposed on the WFM, which fills a space between the first back gate and the second back.

Three dimensional (3D) double gate semiconductor

Before a semiconductor die of a brittle III-V compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing.

III-V compound semiconductor dies with stress-treated inactive surfaces to avoid packaging-induced fractures, and related methods

Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate.

Nanosheet (NS) and fin field-effect transistor (FinFET) hybrid integration

In certain aspects, a duty-cycle monitor includes a first oscillator, and a flop having a signal input, a clock input, and an output, wherein the signal input is coupled to an input of the duty-cycle monitor, and the clock input is coupled to the first oscillator. The duty-cycle monitor also includes a first counter having a count input, an enable input, and a count output, wherein the count input of the first counter is coupled to the first oscillator, and the enable input of the first counter is coupled to the output of the flop. The duty-cycle monitor also includes a second counter having a count input, an enable input, and a count output, wherein the count input of the second counter is coupled to the first oscillator, and the enable input of the second counter is coupled to the output of the flop.

Dynamic aging monitor and correction for critical path duty cycle and delay degradation

Aspects generally relate to a heterojunction bipolar transistor (HBT), and method of manufacturing the same. The HBT including an emitter a first, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter. A collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter. A dielectric coupled to the collector. A first conductive base contact coupled to the base and adjacent to the collector and extending over a base-collector junction, the conductive base contact operative as a field plate.

Heterojunction bipolar transistor with field plates

This patent disclosure provides various embodiments of a client-server based digital video playback system and technique. In one aspect, a process for playing internet/online videos on a user device is disclosed. This process can begin by sending a video playback request for playing an online video to the server, wherein the video playback request includes a device type and a browser type of the user device. Next, the process receives a set of video playback addresses and a set of video playback configuration files from the server, wherein the set of video playback addresses and the set of video playback configuration files are generated based on the device type and the browser type. The process subsequently selects a video playback address from the set of video playback addresses corresponding to a transcoded version of the online video that matches a device version and a browser version of the user device. The process next obtains the transcoded version of the online video from the selected video playback address, and plays the obtained video on the user device.

Method and system for playing digital videos on user devices

Growing community of inventors

San Diego, CA, United States of America

Bin Yang