Bitblitz Communications, Inc.

Hewlett-packard Company

Intersil Corporation

Xdx, Inc.

Bin Wu

Kirk E Fry

Richard Clayton Walker

Steven Rosenberg

Dong Zheng

Russell L Dedrick

Yue-Hong Sutu

Manoj N Rana

The invention presents methods of using splice variants and reagents thereof for diagnosing and monitoring the status of transplants and immune disorders including diagnosing, monitoring and predicting transplant rejection or non-rejection, steroid responsiveness, and onset or flare of immune disorders.

Methods and compositions for diagnosing and monitoring the status of transplant rejection and immune disorders

A phase-locked loop includes a phase detector which receives an input signal and a first internal periodic signal and provides a phase signal indicative of a phase difference between the input signal and the internal signal. A rotator then receives the phase signal and provides first and second periodic signals each having a frequency that is a function of the phase difference, the first and second periodic signals being 90 degrees out of phase with each other. An interpolator circuit then linearly combines the first and second periodic signals with third and fourth periodic signals to provide the first internal periodic signal. The interpolator circuit may provide a second internal periodic signal that is 90 degrees out of phase relative to the first internal periodic signal. The phase-locked loop may further include a low-pass filter provided between the phase detector and the rotator.

Phase-locked loop with analog phase rotator

A detector compares a first bit of a bit stream to a first bit of a pattern. If the first bit of the bit stream and the first bit of the pattern are the same, another detector is allowed to read a second bit of the bit stream and compare it to a second bit of the pattern. This continues until all bits of the pattern are detected. By performing the comparison as each bit of the bit stream arrives on a node, the present detectors are able to detect bit patterns in high-speed bit streams.

High-speed bit-pattern detector

A method and a circuit detect the presence of a high-speed signal, such as a high-speed differential signal, based on a software-programmable signal amplitude threshold. In one embodiment, when the amplitude threshold is exceeded, a current is generated to charge a capacitor. The voltage on the capacitor is compared to a second pre-set voltage in a low-speed comparator, which provides an output voltage indicating detection of the high-speed signal.

High speed differential signal detection

An N-way Circular Phase Interpolator interpolates the N phases of a reference clock signal to generate a tunable clock. By using more than two phases for interpolation, high excess frequencies as well as high precision (i.e. small jitter) are achieved. The N-way Circular Phase Interpolator provides for analog filtering in the phase domain, which attenuates the out-of-band phase noises thus further reducing the output jitter.

N-way circular phase interpolator for generating a signal having arbitrary phase

This invention provides a simple yet robust solution to the phase-locked loop frequency acquisition problem in clock and data recovery circuits by using a frequency detector with a deadband, which is constructed in part with an oversampling rotational frequency detector.

Oversampling rotational frequency detector

A floating clock data recovery circuit may be positioned anywhere in a chain of nodes. An N+1 length series of port bypass circuits are connected such that the output port of one is connected to the input of the next port bypass circuit. N is the number of desired nodes. One of the series of port bypass circuits will be used to 'control' the positioning of the signal conditioning circuitry. When the control PBC is in operation, the loop is 'broken' at that node. As a result, the signal conditioning circuitry may be placed anywhere in the chain of nodes.

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San Jose, CA, United States of America

Bin Wu