Vanguard International Semiconductor Corporation

Vanguard Semiconductor Corp.

Bin Liu

Chao-Ming Koh

Fu-Liang Yang

Wen-Jya Liang

Erik S Jeng

Yeh-Sen Lin

Yu-Chun Ho

Ming-Horn Tsai

Shih-Yin Lan

Chau-Jen Kuo

A method for planarizing DRAM cells comprising the steps of providing a silicon substrate having a field oxide layer, an oxide layer and a capacitor formed thereon, then forming a first dielectric layer over the substrate. Next, portions of the first dielectric layer is etched back to form a spacer layer, and then a second dielectric layer is formed over the spacer layer. Thereafter, an insulating layer is formed over the second dielectric layer. Finally, the insulating layer is fully etched back to form a third dielectric layer.

Method for planarizing DRAM cells

A method for manufacturing a stacked capacitor having fin-shaped electrodes with increased capacitance on a dynamic random access memory (DRAM) cell, was achieved. The invention eliminates the need for a silicon nitride etch stop layer, which is known to cause stress in the substrate and lead to defects. The capacitor bottom electrodes having fin shaped portions is fabricated by depositing a multilayer of alternate layers of silicon oxide and doped polysilicon on a partially completed DRAM device having FETs. After forming, with single masking step, the node contacts to the substrate in the multilayer and depositing another doped polysilicon layer, the polysilicon layers and oxide layer are patterned to form the electrodes. An important feature of this invention is that the patterned multilayer is etched to the silicon oxide layer over the bottom polysilicon layer and then the silicon oxide layer(s) are isotropically etched (e.g. in HF) to form the fin capacitor. The fin structure is then used as a mask to anisotropically etch the bottom polysilicon layer, and thereby complete and electrically isolate the bottom fin-shaped electrodes. The capacitor is completed by forming the inter-electrode dielectric and depositing a top electrode layer.

Method of manufacturing a stacked capacitor having a fin-shaped storage

The present invention is a method of manufacturing crown shape capacitors in the semiconducter memories. Using a single step etching to farbricate the capacitor in a DRAM cell. The method can form side wall polymers and etching byproductions on the surface of the first polysilicon, using the side wall polymers and the etching byproductions as a mask to form the crown shape capacitors with pillars. Moreover, this present invention can form the crown shape structure and pillars in the same step, the crown shape structure and the pillars increase the surface area of the capacitor. Therefore the present invention will increase the performance of the capacitor.

Method of manufacturing a crown shape capacitor in semiconductor memory

This present invention is a method of fabricating a semiconductor memory cell in a DRAM. This invention utilizes a inter plug technique and nitride sidewall spacers to improve deep node contact etching damage and reduce the number of mask steps for typical landing pad processes. Thus, the method of this invention allows the manufacture of a semiconductor memory cell that reduces the difficulties due to the high aspect ratio of the contact hole of a storage node.

Method for fabricating a semiconductor memory cell in a DRAM

A method for planarizing a high step-height integrated circuit structure within an integrated circuit. There is first formed upon a semiconductor substrate a high step-height integrated circuit structure. Formed then adjoining the high step-height integrated circuit structure is a patterned Global Planarization Dielectric (GPD) layer. There is then formed upon the exposed surfaces of the semiconductor substrate, the high step-height integrated circuit structure and the patterned Global Planarization Dielectric (GPD) layer a reflowable dielectric layer. Finally, the reflowable dielectric layer is reflowed.

Method for planarizing high step-height integrated circuit structures

A method for photo-exposing a blanket conformal photosensitive layer upon a high step height topography substrate layer. There is first provided a high step height topography substrate layer having a blanket conformal photosensitive layer formed thereupon. The high step height topography substrate layer has a first region having a first step height separated from a third region having a third step height by a second region having a second step height. The second step height is intermediate to the first step height and the third step height. The blanket conformal photosensitive layer is photo-exposed to form a first pattern upon the first region and the second region through use of a first reticle and a first photo-exposure condition. The first photo-exposure condition provides a first depth of focus suitable for at least the first region. In a separate process step, the blanket conformal photosensitive layer is photo-exposed to form a second pattern upon the second region and the third region through use of a second reticle and a second photo-exposure condition. The second photo-exposure condition provides a second depth of focus suitable for at least the third region. The first pattern upon the second region and the second pattern upon the second region overlap.

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Taipei, Taiwan

Bin Liu