Marvell International Limited

Marvellworld Trade Ltd.

Nestec S.a.

Bin Jiang

Sang Kong Chan

Pantas Sutardja

Oscar M Siguenza

Devang Trivedi

Hsien-Chih Chao

Check Woo Foo

Stefan Kasapis

Lee Wah Koh

Aspects of the disclosure provide a circuit. The circuit includes a switch and a switch controller. The switch is between a first node that receives a first power supply and a second node, and is controlled to couple/decouple the second node with the first node to switch on/off a second power supply at the second node. The switch controller is configured to generate a switch control signal to control a charging current flowing through the switch to switch on the second power supply.

Method and apparatus for power switching

A level shifter circuit for shifting from a first voltage level technology (such as 0.9 volt) to a second level voltage technology (such as 3.3 volt) with increased switching speed. The increased speed is achieved by adding a boost circuit to the pull-up transistors to boost the switching speed and shut itself down after the transition. The level shifter circuit does not require intermediate level transistors or intermediate level voltage sources.

High speed level shifter circuit in advanced CMOS technology

An interface driver circuit includes a plurality of delay cells. Each delay cell includes a data input, a delayed data output configured to communicate with the data input of an adjacent one of the plurality of delay cells. A delay time input is configured to set a delay value between receiving data at the data input and generating the delayed data output. A plurality of predrivers is configured to receive an output enable signal. A plurality of predrivers is configured to receive a corresponding one of the plurality of delayed data outputs. A plurality of predrivers is configured to generate a predriver output signal based on the output enable signal and the corresponding one of the plurality of delayed data outputs. The output enable signal enables and disables the plurality of predrivers and is independent of data of each delayed data output.

Slew rate control circuit for small computer system interface (SCSI) differential driver

An interface driver circuit comprises N cascaded delay cells, each including a data bit input, a delayed data bit output that communicates with the data bit input of an adjacent one of the N cascaded delay cells, and a delay time input that sets delay values between receiving data at the data bit input and generating the delayed data bit output. N predrivers receive an output enable signal that is independent of the data, receive a corresponding one of the N delayed data bit outputs and generate a predriver output signal based on the output enable signal and the corresponding one of the N delayed data bit outputs.

A small computer system interface (SCSI) driver circuit having a programmable slew rate comprises N cascaded delay cells each including a data bit input, a delayed data bit output that communicates with the data bit input of an adjacent one of the N cascaded delay cells, and a delay time input that receives a programmable delay time value for setting a variable delay between receiving data at the data bit input and generating the delayed data bit output. N predrivers receive an output enable signal and a corresponding one of the N delayed data bit outputs and generate a predriver output signal based on the output enable and the corresponding one of the N delayed data bit outputs. N drivers have inputs that receive predriver output signals from corresponding ones of the N predrivers. An output port communicates with outputs of the N drivers.

Growing community of inventors

Singapore, Singapore

Bin Jiang