Intel Corporation

International Business Machines Corporation

Nvidia Corporation

Bimal Poddar

Thomas A Piazza

Rahul P Sathe

Harald Jean Smit

Prasoonkumar Surti

Jon N Hasselgren

Peter L Doyle

Thomas Winters Fox

Michael I Gold

Donghan Ryu

Xiao Bo Zhao Zhang

Samuel Reed Koser

Subramaniam M Maiyuran

Tomas G Akenine-Moller

Michael Apodaca

Carl Jacob Munkberg

Gordon Clyde Fossum

Avinash Seetharamaiah

Robert L Farrell

Saurabh Sharma

Kalyan Kumar Bhiravabhatla

Iliese Claire Chelstowski

Paul A Johnson

Harri Syrja

Kevin Rogovin

Alice Elizabeth Putney

John Joseph Lawless

Approaches in accordance with various embodiments can reduce scheduling delays due to concurrent processing requests, as may involve VSyncs in multi-streaming systems. The software synchronization signals can be staggered relative to each other by offsetting an initial synchronization signal. These software synchronization signals can be readjusted over time such that each synchronization signal maintains the same relative offset, as may be with respect to other applications or containers.

Staggered software synchronization

Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

Optimizing for rendering with clear color

Various embodiments are generally directed to techniques for reducing storage access bandwidth requirements in retrieving a texture image from a storage for applying textures to rendered objects by rendering the texture image itself into the storage to reduce the storage space in which the texture image is stored and to arrange portions of the texture image to be retrieved with fewer accesses. A device to render images includes a processor component; a color analyzer to determine a clear color of a texture image stored as source texture data; and a rendering routine to render the texture image into a storage as reduced texture data, the rendering routine to selectively store in the reduced texture data pixel color values retrieved from the source texture data that are associated with pixels of the texture image not colored with the clear color. Other embodiments are described and claimed.

Techniques for reducing accesses for retrieving texture images

The power consumption of processor-based devices may be reduced by reducing the consumption of power during graphics processing. In some embodiments, the precision of pixel shading in parts of images where artifacts are less objectionable may be reduced. For example, in areas the user is not directly looking at, precision may be reduced to save power. At the same time, because a person is not focusing on those regions, even if usually perceptible artifacts occur because of the reduced precision, an overall pleasing depiction may be achieved.

Variable precision shading

In position-only shading, two geometry pipes exist, a trimmed down version called the Cull Pipe and a full version called the Replay Pipe. Thus, the Cull Pipe executes the position shaders in parallel with the main application, but typically generates the critical results much faster as it fetches and shades only the position attribute of the vertices and avoids the rasterization as well as the rendering of pixels for the frame buffer. Furthermore, the Cull Pipe uses these critical results to compute visibility information for all the triangles whether they are culled or not. On the other hand, the Replay Pipe consumes the visibility information to skip the culled triangles and shades only the visible triangles that are finally passed to the rasterization phase. Together the two pipes can hide the long cull runs of discarded triangles and can complete the work faster in some embodiments.

Position-only shading pipeline

According to some embodiments of the present invention, pixel throughput may be improved by performing depth tests and recording the results on the granularity of an input geometry object. An input geometry object is any object within the depiction represented by a primitive, such as a triangle within an input triangle list or a patch within an input patch list.

Recording the results of visibility tests at the input geometry object granularity

The introduction of an 'out-of-memory' marker in the sorted tile geometry sequence for a tile may aid in handling out-of-memory frames. This marker allows hardware to continue rendering using the original data stream instead of the sorted data stream. This enables use of the original data stream allows the system to continue rendering without requiring any driver intervention. During the visibility generation/sorting phase, the number of memory pages required for storing the data for a rendering pass is continuously tracked. This tracking includes tracking the pages that are required even if the hardware had not run out-of-memory. This information can be monitored by a graphics driver and the driver can provide more memory pages for the system to work at full efficiency.

Dynamically managing memory footprint for tile based rendering

A mechanism is described for dynamically optimizing color buffer clear performance in graphics processing units. A method of embodiments, as described herein, includes allocating and initializing a first set of control bits associated with a framebuffer in a graphics processing unit (GPU), and rendering a first frame, wherein the first set of control bits are associated with the first frame. The method may further include allocating a second set of control bits associated with a second frame, and rendering the second frame. The method may further include facilitating an expedited resolve operation of the second frame based on a frame-to-frame coherence associated with the first and second frames.

Exploiting frame-to-frame coherence for optimizing color buffer clear performance in graphics processing units

Various embodiments are generally directed to an apparatus, method and other techniques to determine color information for multiple graphical layers of a graphical display at a location of a pixel, and to determine a pixel color information for the pixel at the location based on the color information for each of the multiple graphical layers.

Techniques for reducing memory bandwidth for display composition

Apparatus, systems and methods for handling portrait mode oriented display surfaces without requiring expensive hardware in the display sub-system are disclosed. For example, an apparatus is disclosed such that the rendering of graphics data to the portrait mode display surfaces is redirected at rendering time such that there is no need for adding complicated hardware in the display part of the graphics adapter in order to handle conventional displays&#x2014;all of which have no circuitry to deal with data natively stored in a portrait mode surface. Additionally, an apparatus to handle direct surface access of a surface through a surface lock which has already been rotated is already described. This can either be done by copying of surface data or by an optimized proposed apparatus which eliminates this copy. Other implementations are also disclosed.

Rotated rendering and locking support for tablet computers and portrait displays

A method is described that involves redefining a primitive surface to create a redefined primitive surface. The redefining involves clipping a first edge of the primitive surface to a second edge of a displayable screen area. The first edge of the primitive surface extends outside a guard band region prior to the clipping. The guard band region surrounds the displayable screen area. The clipping causes the redefined primitive surface to have an edge running within the guard band that the primitive surface does not have.

Growing community of inventors

El Dorado Hills, CA, United States of America

Bimal Poddar