E-systems, Inc.

Billy R Poston

Robert S Gordy

David E Sanders

Carl F Andren

Ramon P Chambers

Stuart L Atkinson

Arthur M Richard

Charles F Pavey

A method for establishing and maintaining a nodal network in a communication system is described using a network connectivity matrix at each node of the network. The network connectivity matrix has a plurality of channels each corresponding to a node of the network and storing nodal information about the connectivity status of the node in the network. Each channel (row) of the network connectivity matrix at each node includes a first field for storing data indicating whether a usable line-of-sight (LOS) transmission path exists between the node and each other node of the network, a second field for storing data indicating when the row was last revised, a third field for storing the identification of the most recent transmission received by the node and a fourth field for storing data indicating a quality of the transmission path between the node and each node within LOS of the node. A method of routing information uses the network connectivity matrix to control distribution of messages throughout the network in a global fashion as well as between specific source and destination nodes.

Method for establishing and maintaining a nodal network in a

A method and apparatus is disclosed for decoding a redundantly coded digital signal wherein each information character is coded with a plurality of signal elements. Each of the signal elements is sampled by an analog to digital converter (110) and the resulting sample value is transmitted to an adder (114). The sampled value is added to an accumulated sum which is received from a storage circuit (128). The sum of the sampled value and the accumulated sum is transmitted through a selector switch (120) to both a decision circuit (126) and the storage circuit (128). After the last of the redundantly coded signal elements is sampled and the sampled values included within the accumulation sum, the state of the information character is determined by the decision circuit (126). Switch (120) then enters a null data set to reset the accumulated sum to zero for processing the next group of redundantly coded signal elements.

Apparatus for decoding redundant interleaved data

A digital pulse detector circuit having a selectable false alarm rate receives an analog input signal containing periodic correlation pulses in a background of noise. The input signal is sampled and digitized to produce a series of digital input samples which are taken for regular time slots within a series of time frames. Each of the digital input samples is summed with a previously stored digital summation sample to produce a new summation digital sample that replaces the summation sample read out of memory to produce the new summation sample. The new digital summation sample is compared to a threshold value to produce a signal confirmed signal to indicate detection of the correlation pulse. When a set number of summation steps are carried out for a particular time slot and the summation value for that time slot has not exceeded the threshold value, that time slot is reset to zero to eliminate accumulated noise. The threshold values of the integrated pulses can be set at the threshold detector to enable the operator to select the false alarm rate.

Digital pulse detector circuit having selectable false alarm rate

Frequency indication pulses are applied to comparison and feedback logic for the identification of a frequency in a selected frequency band. The comparison and feedback logic is part of an identification circuit that includes a main memory for storing representations of frequency values that is coupled to the comparison and feedback logic by data transfer gating. Control logic coupled to the data transfer gating and main memory provides shift pulses, clock pulses and control signals to sequence the operation of the main memory and comparison and feedback logic. Interval timing and control logic receives from the RF section of the compressive receiver a compare signal, a manual set signal and clock pulses to generate inhibit and enable signals for the comparison and feedback logic, and the control logic. When a comparison in the comparison and feedback logic between a received frequency indication pulse and a memory bit from the main memory indicates the presence of a new frequency, frequency value information, in the form of a sixteen bit data word, is transferred to interface logic and interface memory that encodes a digital word representing a specific frequency occurring within the time constrained subinterval. This digital word representation of a specific frequency is applied to an interface bus as frequency data available to the other sections of the compressive receiver.

Frequency identification circuit

Improved acquisition of signals in a Gaussian noise environment is achieved by applying the output of a correlator (14) to a threshold detector (12). A correlation pulse output from the threshold detector (12) and the output of the correlator (14) are input to a false alarm processor (10) that includes multiple correlation checking channels (22). Each correlation checking channel (22) is assigned to sample an input at various points over a selected interval by an enable pulse generated at the output of select logic (30). Each correlation checking channel (22) includes correlation check enable logic (34), a blanking generator (36), and a confirmation logic (42). In the confirmation logic (42) samples of the analog input are taken at discrete times and integrated over a preselected number of intervals. If this integrated value exceeds a threshold level during the integration interval, the analog input signal is considered valid and a 'signal confirmed' pulse is generated and gated through a gate NAND (44) onto a signal confirm line 28.

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St. Petersburg, FL, United States of America

Billy R Poston