Advanced Micro Devices Corporation

Altera Corporation

Bill Yowjuang Liu

Paul Raymond Besser

Scott Allan Bell

Olov B Karlsson

Peter John McElheny

Hamid Partovi

Wei Long

Chun Jiang

Francois Gregoire

Priya Selvaraj

A method of fabricating transistors on a semiconductor substrate is disclosed according to a first embodiment of the present invention. Gate dielectrics of equal thickness are provided to a first and second transistor on the semiconductor substrate. A polysilicon doping level of the first transistor is varied with a polysilicon doping level of the second transistor.

Polysilicon gate doping level variation for reduced leakage current

Air gap insulation regions are formed selectively within high parasitic capacitance regions in which conductive lines are closely proximate and generates an intolerable amount of parasitic capacitance. The selective formation of air gap insulation regions improves circuit performance by reducing the parasitic capacitance and device reliability by reducing the stress fracture problem of conventional air gap insulation schemes.

Selective air gap insulation

A semiconductor arrangement and method of forming silicide regions includes conformally depositing a reducing material layer on a silicon substrate. A refractory metal layer is then conformally deposited on the reducing material layer. Annealing is then performed to form a refractory metal silicide layer on the silicon substrate. The metal silicide layer is a cobalt silicide and the reducing material layer includes at least one of tantalum, magnesium, aluminum or calcium. The reducing material reduces native oxide on a silicon substrate to allow the cobalt silicide to form.

Method of forming cobalt silicide

The gate structure of the MOSFET of the present invention is formed to have a longer length toward the top of the gate structure such that a spacer having a substantially rectangular shaped is formed at the sidewalls of the gate structure. For fabricating a gate structure of a field effect transistor on a semiconductor substrate, a layer of gate structure material is deposited on the semiconductor substrate. The composition of the layer of gate structure material is adjusted along a depth of the layer of gate structure material for a slower etch rate toward a top of the layer of gate structure material that is further from the semiconductor substrate. The gate structure is then formed by patterning and etching the layer of gate structure material. The slower etch rate toward the top of the layer of gate structure material results in a longer length toward a top of the gate structure that is further from the semiconductor substrate. Spacer dielectric is deposited conformally on exposed surfaces of the gate structure. The spacer dielectric is anisotropically etched such that the spacer dielectric remains on sidewalls of the gate structure. The longer length toward the top of the gate structure results in a substantially rectangular shaped spacer dielectric remaining on the sidewalls of the gate structure. The present invention may be used to particular advantage when the gate structure and the spacer having the rectangular shape are formed as part of a field effect transistor such as a MOSFET.

Fabrication of a gate structures having a longer length toward the top for formation of a rectangular shaped spacer

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San Jose, CA, United States of America

Bill Yowjuang Liu