Altera Corporation

Bill W Bereza

Shoujun Wang

Tad Kwasniewski

Haitao Mei

Mashkoor Baig

Sergey Yuryevich Shumarayev

Rakesh H Patel

Wilson Wong

Chong H Lee

High-speed serial data transceiver circuitry on a programmable logic device ('PLD') includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop ('PLL') circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

Heterogeneous transceiver architecture for wide range programmability of programmable logic devices

Equalization circuitry that includes an analog equalizer and a decision feedback equalizer (DFE) is provided for high-speed backplane data communication. The analog equalizer reduces the number of taps that are required by the DFE, which lessens the error propagation of the DFE. Furthermore, the DFE includes a summing circuit and flip-flop circuitry. The flip-flop circuitry may be used as part of a phase detector by clock and data recovery circuitry. The summing circuit may further be embedded into the flip-flop circuitry to reduce the feedback path delay, thereby allowing for higher speed operation. The DFE may be extended to multiple taps by including additional flip-flops.

Methods and apparatus for equalization in high-speed backplane data communication

A clock data recovery loop that can be used over a wide range of data rates and maintain second-order behavior includes a nonlinear (e.g., Bang-Bang) phase detector, a charge pump, an RC loop filter, and signal generator (e.g., a voltage controlled oscillator (VCO)). At low data rates, the loop may be operated with the charge pump and loop filter with stable second-order behavior, with the resistor R of the loop filter serving as a proportional path. A separate proportional path is also provided that provides phase detector output directly to a control input of the VCO, while the resistor R of the loop filter is also bypassed. As increasing data rates give rise to third-order effects, the separate proportional path may be activated to maintain second-order behavior.

Clock data recovery loop with separate proportional path

Pre-emphasis circuitry and methods for signal transmission provide multiple levels of output signal amplification over one or more baud periods after an input signal transition. The multiple, gradually decreasing levels of output signal amplification reduce power consumption and better approximate the desired signal response.

Multitap fractional baud period pre-emphasis for data transmission

A received clock signal is aligned ('eye centered') with a received data signal by recovering a separate clock from the data signal and comparing and aligning the received clock with the recovered clock by delaying one or both of the received clock and the received data as necessary. After the necessary delays are set, the comparison/alignment circuitry can be turned off, until the next time alignment is necessary, to conserve power. In a multiple channel system, any combination of each received data channel, the received clock, or individual branches of the received clock in each channel can be delayed as necessary. Each channel can have its own comparison/alignment circuitry so that all channels can be aligned simultaneously, or re-usable circuitry can be provided for connection sequentially to each channel where sequential alignment of the channels is fast enough.

Alignment of clock signal with data signal

A dynamic frequency divider circuit with improved leakage tolerance supports a wide frequency range. During the evaluation phase, (1) the input signals can be prevented from changing states, (2) the leakage can be reduced, or (3) both can be implemented to generate the correct output signals. In a architecture-level approach, two dynamic flip-flops can be coupled together. In a circuit-level approach, the dynamic flip-flop can include (1) two additional clocked PMOS transistor added to the inputs of the dynamic flip-flop, or (2) two additional pull-up PMOS transistors to counteract the subthreshold leakage in the NMOS transistors.

Dynamic frequency divider with improved leakage tolerance

An integrated circuit (IC) includes a ring oscillator. One may tune the ring oscillator by controlling a power supply of the ring oscillator. One may further tune ring oscillator by varying a capacitance of at least one varactor. Using the tuning techniques, one may tune the output frequency of the ring oscillator to a desired frequency.

Apparatus and method for wide tuning-range ring oscillators

Possible deficiencies of a communication link are detected and automatically counteracted, at least to some degree. The deficiencies addressed can include phase shift and attenuation compensation. The counter-action can include adjustment of pre-emphasis given a signal applied to the communication link and/or adjustment of equalization given a signal received from the communication link.

Adaptive communication methods and apparatus

Circuitry and methods allow signal detection based entirely on differential voltage pairs. An incoming differential data signal is processed by separate full-wave rectifiers to extract high and low peak voltage envelopes. The rectifiers utilize negative feedback to ensure accurate envelope detection, and can detect peaks regardless of incoming signal polarity. The extracted envelopes are compared to a differential pair of threshold voltages. If the envelope signals have a smaller voltage difference than that of the threshold signals, the final output of the detector indicates that a loss-of-signal condition has occurred. Fully differential operation makes the detector independent of common-mode voltage, and thus more robust.

Differential signal detector methods and apparatus

A recovered clock signal is aligned ('eye centered') with a data signal from which it is recovered by intentionally varying one of the factors or parameters that causes misalignment. For example, if a loop circuit (i.e., a phase-locked loop or a delay-locked loop) is used to recover the clock signal, charge pump current mismatch in the charge pump of the loop circuit is normally one factor in clock-data misalignment, and is also a parameter that can be manipulated. During a test mode, the current mismatch can be varied to obtain the best error rate, which signifies the best clock-data alignment. The test mode can be implemented using built-in self-test circuitry already on the device to transmit test data and then to receive it and analyze it for errors.

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Nepean, Canada

Bill W Bereza