Teradyne, Inc.

Bill Sopkin

Peter A Reichert

Chris Reed

A memory control circuit is disclosed for use in a data path of a failure capture circuit to selectively control the storage of failure information associated with a pin of a device-under-test. The memory control circuit includes a memory controller operative to generate a store signal in response to a failure control signal and a semiconductor memory having a control input coupled to the controller for receiving the store signal. The memory controller operates in response to the store signal to write failure information associated with a particular failure control signal. Disable logic in the memory control circuit is operative according to predetermined conditions for selectively inhibiting the delivery of the failure control signals to the memory controller.

Fail array memory control circuit with selective input disable

A pattern generator for use in a memory tester to provide packet address and data signals to a packet-based memory-under-test is disclosed. The pattern generator includes an address source for generating an external packet memory address signal. The external packet memory address signal represents a plurality of addressable memory elements in the memory-under-test. A plurality of data generators are disposed in parallel relationship and coupled to the output of the address source to receive at least a portion of the packet memory address signal. Each of the data generators has logic operative to derive an internal address from the packet address. The internal address corresponds to an individual memory element within the memory under test. A sequencer is disposed at the outputs of the data generators to distribute the data generator outputs in a packet waveform for application to the memory-under-test.

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Oxnard, CA, United States of America

Bill Sopkin