Compaq Computer Corporation, Inc.

Bill Skelton

Randy M Bonella

Mark E Taylor

Joseph P Miller

Roy E Thoma, Iii

A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.

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Cypress, TX, United States of America

Bill Skelton