Omnivision Technologies, Inc.

Cypress Semiconductor Corporation

Silicor Materials Inc.

Omnivision Technologies, Inc.omnivision Technologies, Inc.

Bill Phan

Duli Mao

Yuanliang Liu

Seong Yeol Mun

Keiji Mabuchi

Dyson Hsinchih Tai

Zhiqiang Lin

Gang Chen

Dajiang Yang

Alireza Bonakdar

Oray Orkun Cellek

Sing-Chung Hu

Xin Ru Wang

Hui Zang

Heesoo Kang

Siguang Ma

Sohei Manabe

Helmut Puchner

Qin Wang

Johannes Solhusvik

Trygve Willassen

Woon Il Choi

Yifei Du

Vincent Venezia

Boyd Fowler

Shiyu Sun

Alain Paul Blosse

Yuanwei Zheng

Chengming Liu

Badrinath Padmanabhan

Martin Kaes

Kevin Jang

Jean Patrice Rakotoniaina

Cynthia Sun Yee Lee

Chiao-Ti Huang

Omar Sidelkheir

Jaejune Jang

Takeshi Takeda

Xianfu Cheng

Renhua Zhang

John Gorman

An image sensor comprising a semiconductor substrate, a plurality of photodiodes, a multilayer reflective stack, and a dielectric layer is disclosed. The plurality of photodiodes is disposed within the semiconductor substrate and includes a first photodiode and a second photodiode adjacent to the first photodiode. The multilayer reflective stack comprises a first material having a first refractive index and a second material having a second refractive index. The dielectric layer has a third refractive index and is disposed between the first photodiode and the multilayer reflective stack. The first material is disposed between the second material and the dielectric layer. The first refractive index is greater than the second refractive index and the third refractive index.

Multilayer reflective stack for reducing crosstalk in split pixel image sensors

Image sensors with improved memory effect are disclosed herein. In one embodiment, a method for reducing image lag associated with a pixel included in a plurality of pixels is described. The pixel includes a photodiode, a first floating diffusion coupled to the photodiode through a transfer transistor, a second floating diffusion coupled to the first floating diffusion through a dual floating diffusion transistor, and a lateral overflow integration capacitor coupled between the second floating diffusion and a bias voltage source. The lateral overflow integration capacitor is further coupled to a pixel reference voltage source through a reset transistor. Operation of the pixel comprises an idle period and an integration period after the idle period. The method also includes configuring the lateral overflow integration capacitor to be either zero-biased or forward-biased during the idle period.

Operation method to mitigate lag issue with high k metal-insulator-metal (MIM) capacitor

Image sensors, isolation structures, and techniques of fabrication are provided. An image sensor includes a source of electromagnetic radiation disposed on a substrate, a pixel array disposed on the substrate and thermally coupled with source of electromagnetic radiation, and an isolation structure disposed on the substrate between the source of electromagnetic radiation and the pixel array. The isolation structure can define a first reflective surface oriented on a first bias relative to a lateral axis of the pixel array and a second reflective surface oriented on a second bias relative to the lateral axis. The isolation structure can be configured to attenuate residual electromagnetic radiation reaching a proximal region of the pixel array by pairing a first reflection and a second reflection of the electromagnetic radiation by the first reflective surface and the second reflective surface.

Image sensor diagonal isolation structures

An image sensor includes a photodiode disposed in a semiconductor substrate having a first surface and a second surface opposite to the first surface. A floating diffusion is disposed in the semiconductor substrate. A transfer transistor is configured for coupling the photodiode to the floating diffusion. The transfer transistor includes a vertical transfer gate extending a first depth in a depthwise direction from the first surface into the semiconductor substrate. A transistor is coupled to the floating diffusion. The transistor includes: a planar gate disposed proximate to the first surface of the semiconductor substrate; and a plurality of vertical gate electrodes, each extending a respective depth into the semiconductor substrate from the planar gate in the depthwise direction. The respective depth of at least one of the plurality of vertical gate electrodes is the same as the first depth of the vertical transfer gate.

Transistors having increased effective channel width

A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion. The transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a reset voltage and the floating diffusion. A plurality of capacitor-switch pairs is coupled between the reset transistor and a bias voltage source. Each of the plurality of capacitor-switch pairs includes a lateral overflow integration capacitor (LOFIC) and a switch transistor coupled to the LOFIC.

High K metal-insulator-metal (MIM) capacitor network for lag mitigation

A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a pixel voltage source and the floating diffusion. A lateral overflow integration capacitor (LOFIC) network includes a first LOFIC coupled between the floating diffusion and the first bias voltage source, and a second LOFIC coupled between the floating diffusion and the second bias voltage source. The first LOFIC is configured to be forward biased and the second LOFIC is configured to be reverse biased at an end of an integration period, and image charge discharged from the first LOFIC and image charge discharged from the second LOFIC compensate each other during a readout period.

Optimized pixel design for mitigating MIM image lag

A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion. The transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a reset voltage and the floating diffusion. A lateral overflow integration capacitor (LOFIC) network is coupled between the reset transistor and a bias voltage source. The LOFIC network includes a main LOFIC coupled between the reset transistor and the bias voltage source, and a plurality of subordinate capacitor-switch pairs, each including a subordinate LOFIC and a switch transistor coupled to the subordinate LOFIC. Each of the plurality of subordinate capacitor-switch pairs is coupled between the reset transistor and the bias voltage source.

LOFIC circuit for in pixel metal-insulator-metal(MIM) capacitor lag correction and associated correction methods

A reduced cross-talk pixel-array substrate includes a semiconductor substrate, a buffer layer, a metal annulus, and an attenuation layer. The semiconductor substrate includes a first photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the first photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the first photodiode region. The buffer layer is on the back surface and has a feature located above the first photodiode region with the feature being one of a recess and an aperture. The metal annulus is on the buffer layer and covers the trench. The attenuation layer is above the first photodiode region.

Suppressed cross-talk pixel-array substrate and fabrication method

An image sensor comprises a first photodiode region and circuitry. The first photodiode region is disposed within a semiconductor substrate proximate to a first side of the semiconductor substrate to form a first pixel. The first photodiode region includes a first segment coupled to a second segment. The circuitry includes at least a first electrode associated with a first transistor. The first electrode is disposed, at least in part, between the first segment and the second segment of the first photodiode region such that the circuity is at least partially surrounded by the first photodiode region when viewed from the first side of the semiconductor substrate.

Pixel layout with photodiode region partially surrounding circuitry

SiGe photodiode for crosstalk reduction. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor material. Each pixel includes a plurality of photodiodes. The plurality of pixels are configured to receive an incoming light through an illuminated surface of the semiconductor material. Each pixel includes a first photodiode comprising a silicon (Si) material; and a second photodiode having the Si material and a silicon germanium (SiGe) material.

SiGe photodiode for crosstalk reduction

CMOS image sensor with LED flickering reduction and low color cross-talk are disclosed. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array that is disposed in a semiconductor substrate. Each pixel includes a plurality of large subpixels (LPDs) and at least one small subpixel (SPD). A plurality of color filters are disposed over individual subpixels. Each individual SPD is laterally adjacent to at least one other SPD.

CMOS image sensor with LED flickering reduction and low color cross-talk

A flicker-mitigating pixel-array substrate includes a semiconductor substrate and a metal annulus. The semiconductor substrate includes a small-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region. The metal annulus (i) at least partially fills the trench, (ii) surrounds the small-photodiode region in the cross-sectional plane, and (iii) extends above the back surface. A method for fabricating a flicker-mitigating pixel-array substrate includes forming a metal layer (i) in a trench that surrounds the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region and (ii) on the back-surface region. The method also includes decreasing a thickness of an above-diode section of the metal layer located above the back-surface region.

Flicker-mitigating pixel-array substrate

Image sensors include a photodiode disposed in a semiconductor substrate and a transistor operatively coupled to the photodiode. At least three substrate trench structures are formed in the semiconductor substrate, defining two nonplanar structures, each having a plurality of sidewall portions. An isolation layer includes at least three isolation layer trench structures, each being disposed in a respective one of the three substrate trench structures. A gate includes three fingers, each being disposed in a respective one of the three isolation layer trench structures. An electron channel of the transistor extends along the plurality of sidewall portions of the two nonplanar structures in a channel width plane.

Image sensors include a photodiode disposed in a semiconductor substrate and a transistor operatively coupled to the photodiode. The transistor includes a nonplanar structure disposed in the semiconductor substrate, which is bounded by two outer trench structures formed in the semiconductor substrate. Isolation deposits are disposed within the two outer trench structures formed in the semiconductor substrate. A gate includes a planar gate and two fingers extending into one of two inner trench structures formed in the semiconductor substrate between the nonplanar structure and a respective one of the two outer trench structures. This structure creates an electron channel extending along a plurality of sidewall portions of the nonplanar structure in a channel width plane.

A pixel cell includes a plurality of subpixels to generate image charge in response to incident light. The subpixels include an inner subpixel laterally surrounded by outer subpixels. A first plurality of transfer gates disposed proximate to the inner subpixel and a first grouping of outer subpixels. A first floating diffusion is coupled to receive the image charge from the first grouping of outer subpixels through a first plurality of transfer gates. A second plurality of transfer gates disposed proximate to the inner subpixel and the second grouping of outer subpixels. A second floating diffusion disposed in the semiconductor material and coupled to receive the image charge from each one of the second grouping of outer subpixels through the second plurality of transfer gates. The image charge in the inner subpixel is received by the first, second, or both floating diffusions through respective transfer gates.

Growing community of inventors

San Jose, CA, United States of America

Bill Phan