Texas Instruments Corporation

Bill Kraus

Jarrod Eliason

Yunchen Qiu

Xiao Hong Du

Scott Robert Summerfelt

Hugh Pryor McAdams

Theodore Sidney Moise

This invention is a new CMOS voltage booster () having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN) to charge a boosting capacitor (C) to VDD at the end of each memory access and includes a PMOS FET (MP, MP) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN) is boosted above VDD+Vthn by a small capacitor (C) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C) is pre-charged to VDD by a NMOSFET (MN) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP, MP) is shorted to its source to turn if off during boostenig. Transistor (MP) facilitates boosting the NMOS FET (MN) above VDD.

CMOS voltage booster circuits

This invention is a new CMOS voltage booster () having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN) to charge a boosting capacitor (C) to VDD at the end of each memory access and includes a PMOS FET (MP, MP) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN) is boosted above VDD+Vthn by a small capacitor (C) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C) is pre-charged to VDD by a NMOSFET (MN) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP, MP) is shorted to ists source to turn if off during boostenig. Ttransistor (MP) facilitates boosting the NMOS FET (MN) above VDD.

CMOS voltage booster circuit

This invention is a new CMOS voltage booster () having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. One key idea in this CMOS booster is to use a NMOS FET (MN) to charge the boosting capacitor (C) to VDD at the end of each memory access and to use a PMOS FET (MPMP) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET is boosted above VDD+Vthn by a small capacitor (C) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C) is pre-charged to VDD by a NMOSFET (MN) whose gate is connected to the word line boosting capacitor. The gate of the PMOS FET is shorted to its source to turn it off during boosting.

A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.

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Palmer Lake, CO, United States of America

Bill Kraus