Advanced Micro Devices Corporation

Bill Kai Chiu Kwan

Anthony J Bybell

Robert Bradford Cohen

Frank C Galloway

Tzu-Wei Lin

A processor employs a plurality of fetch and decode pipelines by dividing an instruction stream into instruction blocks with identified boundaries. The processor includes a branch predictor that generates branch predictions. Each branch prediction corresponds to a branch instruction and includes a prediction that the corresponding branch is to be taken or not taken. In addition, each branch prediction identifies both an end of the current branch prediction window and the start of another branch prediction window. Using these known boundaries, the processor provides different sequential fetch streams to different ones of the plurality of fetch and decode states, which concurrently process the instructions of the different fetch streams, thereby improving overall instruction throughput at the processor.

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Austin, TX, United States of America

Bill Kai Chiu Kwan