Advanced Micro Devices Corporation

Globalfoundries Inc.

Bill K Kwan

Erik Schlanger

Atchyuth Gorti

Casey King

Venkat Kuchipudi

Raquel Rozas

David A Kaplan

Nathan Francis Sheeley

Amit Pandey

Eric Swartzendruber

Norm M Hack

Anirudh Kadiyala

Aditya Jagirdar

Chin-Chia Kuo

Scan-based reset utilizes already existing design-for-test scan chains to reset control and logic circuitry upon reset conditions, such as power-up reset. Such utilization eliminates the need for expensive, high fan-out reset trees and per scan cell reset control logic, thus reducing chip area and power consumption. Additional power savings is achieved by controlling clock frequency during reset conditions. Limiting scan cell chain length and providing multiple chains reduces reset latency.

Scan-based reset

The present invention provides a method and apparatus for saving and restoring soft repair information. One embodiment of the method includes storing soft repair information for one or more cache arrays implemented in a processor core in a memory element outside of the processor core in response to determining that a voltage supply to the processor core is to be disconnected.

Method and apparatus for saving and restoring soft repair data

A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.

Scan or JTAG controllable capture clock generation

A video processing apparatus and methodology are implemented as a combination of a processor and a video decoding hardware block to decode video data by performing piecewise processing of overlap smoothing and in-loop deblocking in a macroblock-based fashion. With this approach, a smaller on-board memory may be used for the in-loop filtering operations of the video decoding hardware block. By pipelining the piecewise processing operations, latency in the filtering operations is hidden and the filtering output is smoothed, thereby avoiding the need for bursts of fetching and storing of blocks.

Piecewise processing of overlap smoothing and in-loop deblocking

A video processing apparatus and methodology use a combination of a processor and a video decoding hardware block to decode video data by using a reference block cache memory to perform motion compensation decode operations in the video decoding hardware block. To improve the cache hit rate, each memory access for required reference block(s) is used to fetch one or more additional reference blocks which can be used to improve the cache hit rate with future motion compensation operations. Speculative fetch control logic selects the additional reference blocks by using a frequency history table to accumulate compared motion vector information for a current motion compensation block with motion vector information from previously processed motion compensation blocks.

Macroblock cache

A video processing apparatus and methodology are implemented as a combination of a processor and a video decoding hardware block to decode video data by providing the video decoding block with an in-loop filter and a scratch pad memory, so that the in-loop filter may efficiently perform piecewise processing of overlap smoothing and in-loop deblocking in a macroblock-based fashion which is a much more efficient algorithm than the frame-based method.

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Austin, TX, United States of America

Bill K Kwan