Advanced Micro Devices Corporation

Globalfoundries Inc.

Bill K C Kwan

Daniel William Bailey

Craig D Eaton

Maurice B Steinman

Spencer Montgomery Gold

Atchyuth Gorti

Alexander J Branover

Steven Kommrusch

Guhan Krishnan

Frank P Helms

W Kurt Lewchuk

Matthew J Amatangelo

Paul Mackey

Anirudh Kadiyala

Kevin M Gillespie

Venkat Kuchipudi

Tendy The

A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.

Scan or JTAG controllable capture clock generation

Methods, apparatus, and fabrication processes relating to implementing cyclic redundancy checks (CRCs) in processors, such as CRC32 instructions in x86 computer architectures. A method may comprise extracting a first CRC value from a data packet, performing a carryless operation upon the data packet to determine a second CRC value, and determining that a data error is present in the data packet when the first and second CRC values do not match.

Implementation of CRC32 using carryless multiplier

Methods, apparatus, and fabrication techniques relating to improved propagation of fuse data through an integrated circuit device during scan shift reset. In some embodiments, the methods comprise loading a first value of at least one fuse bit to an integrated circuit device, during a time period when a clock signal having a first frequency is provided to at least one component of the integrated circuit device; disabling a scan shift after the loading of the first value; inactivating the clock signal after the loading of the first value; propagating the first value of the at least one fuse bit to the at least one component of the integrated circuit device; and reactivating the clock signal after the propagation of the first value.

Safe reset configuration of fuses and flops

Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer.

Clock domain data transfer device and methods thereof

A clock generator system () includes a phase locked loop (PLL) (), a first clock generator (), and a second clock generator (). The PLL () includes a first output configured to provide a first clock signal at a first frequency and a second output configured to provide a second clock signal at the first frequency. The second clock signal is out-of-phase with the first clock signal. An output of the first clock generator () is configured to provide a first generated clock signal whose effective frequency is based on both the first and second clock signals and a first mode signal. An output of the second clock generator () is configured to provide a second generated clock signal whose effective frequency is based on both the first and second clock signals and a second mode signal.

Techniques for integrated circuit clock management using multiple clock generators

A processor () includes a clock source (), a central processing unit (CPU) (), and a clock generator (). The clock source () includes an output for providing a periodic clock signal. The CPU () includes an input for receiving a CPU clock signal. The clock generator () includes a first input coupled to the output of the clock source (), a second input for receiving a mode signal that indicates an output frequency, and an output coupled to the input of the CPU (). The clock generator () provides the CPU clock signal using periodic pulse skipping such that the CPU clock signal has a number of transitions over a unit of time corresponding to the output frequency.

Techniques for integrated circuit clock management using pulse skipping

A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.

Method and apparatus for clock cycle stealing

A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.

Selective deactivation of processor cores in multiple processor core systems

An integrated circuit () includes a debug module () and a clock generator (). The debug module () is configured to receive a test pattern and provide a mode signal based on the test pattern. The clock generator () includes a first clock input configured to receive a first clock signal, a second clock input configured to receive a second clock signal, and a mode input configured to receive the mode signal. The first and second clock signals are out of phase and have the same clock frequency. The clock generator () is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.

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Austin, TX, United States of America

Bill K C Kwan