National Semiconductor Corporation

Bill C Wong

Sing W Chin

Ion E Opris

Edison Fong

Hao Yu

Bumha Lee

Satoshi Sakurai

Peter D Capofreddi

A duty cycle correction circuit () for receiving an input clock signal () and generating an output clock signal () having a predetermined duty cycle includes a clock trigger circuit () generating the output clock signal () having a first clock edge triggered from the input clock signal and a second clock edge triggered from a delayed clock signal (); a charge pump circuit () receiving the output clock signal and generating charging and discharging currents for a capacitor (C) where a control voltage develops on the capacitor indicative of the duty cycle error of the output clock signal; a self-track bias circuit () receiving the control voltage and generating first and second bias voltages () in response to the control voltage; and a delay-locked loop circuit () receiving the output clock signal and the first and second bias voltages and generating the delayed clock signal.

Duty cycle correction circuit with small duty error and wide frequency range

A reference voltage buffer circuit () includes first and second transistors (M, M) and first and second resistors (R, R) connected in series between positive and negative power supply voltages and providing a positive reference voltage (Vrp) and a negative reference voltage (Vrn) at the first current handling terminals of the first and second transistors, respectively. A first control voltage (Vg) for driving the first transistor is generated by a first feedback loop and using a positive boosted voltage. A second control voltage (Vg) for driving the second transistor is generated by a second feedback loop and using a negative boosted voltage. The first and second feedback loops establish the first and second control voltages while the positive and negative boosted voltages ensure sufficient drives are provided to the first and second transistors. The reference voltage buffer is capable of fast settling while maintaining a wide reference voltage range.

Fast settling reference voltage buffer with wide reference range

Each stage of a pipeline ADC includes an analog delay cell, a sub-stage ADC, and a multiplying digital-to-analog converter (MDAC). The MDAC includes a sample-and-hold amplifier (SHA) circuit, a summer, a gain stage, and a DAC. The MDAC is arranged in cooperation with the analog delay cell such that the effects of a long comparator decision time under high-speed conditions are minimized. The first SHA, half clock cycle delay cell with unity gain transfer function, samples the input signal during the first clock period, followed by a strobe of the sub-ADC. Substantially half of the clock period can be utilized for the comparison time of the sub-ADC using the described methods. Since decoding is completed before MDAC sampling the first SHA output so that the complete half clock cycle can be arranged for amplifier settling in order to achieve the maximum operating speed with a given amplifier bandwidth.

Pipeline ADC using multiplying DAC and analog delay circuits

An analog to digital converter section for use in an analog to digital converter which includes a converter stage which produces a digital and an residue output. The residue output is applied to an over-range stage which produces a second residue output equal to the first residue output reduced in magnitude by the magnitude of a reference voltage. The over-range stage is capable of operating with a relatively high feedback factor to increase operating speed and with commutated feedback-capacitor switching to reduce differential non-linearity errors.

Algorithmic analog-to-digital converter with reduced differential

A capacitor array-based, successive approximation analog-to-digital signal converter includes a capacitor array with a central coupling capacitor having a unit-value capacitance and two sets of input coupling capacitors having capacitances which are binary weighted multiples of such unit-value capacitance. During the sampling phase, the first set of input coupling capacitors is grounded while the second set of input coupling capacitors is driven by the analog input voltage. During the holding, or conversion, phase, one of the input coupling capacitors in the second set is grounded while each one of the input coupling capacitors in the first set and each one of the remaining input coupling capacitors in the second set is driven by a respective binary multiple of a fixed reference voltage, with each one of such binary multiples corresponding to one of the bits of the successive approximation result.

Split capacitor array for digital-to-analog signal conversion

An error correction technique for high-resolution analog-to-digital converters corrects for both component mismatch and circuit nonlinearity errors by utilizing look-up tables to store mismatch coefficients, which represent the errors introduced by component mismatch, as well as a series of offset and gain coefficients, which are utilized to form a piecewise-linear representation of the error introduced by circuit nonlinearities. The use of an independent gain and offset parameter for each segment of the piecewise-linear representation allows discontinuous functions to be accommodated. This leads to a more efficient implementation since it allows the error introduced by mismatch in the components representing the most significant bits to be included in the piecewise linear table, while separate lookup tables are used for the less significant bits.

Efficient architecture for correcting component mismatches and circuit

The comparison circuitry of a comparator is isolated from noise on the power supply and ground by utilizing transistors operating in the forward-active region to isolate the comparison circuitry. The comparison circuitry is further isolated from random noise spikes by utilizing delay and switching circuitry to control the duration of the comparison.

Growing community of inventors

Milpitas, CA, United States of America

Bill C Wong