Texas Instruments Corporation

Bill Alan Wofford

Binghua Hu

Sameer P Pendharkar

Xinfen Chen

Robert Hung Nguyen

Blake Ryan Pasker

Qingfeng Wang

Damien Thomas Gilmore

Mindricelu P Eugen

Joseph M Ramirez

One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.

Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of manufacture thereof

Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 9&#xb0; or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.

LDMOS transistor double diffused region formation process

A capacitor () is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor () has conductive top and bottom electrodes () and a nonconductive capacitor dielectric (). In one example, the dielectric () includes first and second thin dielectric layers () that sandwich a layer of antireflective material (). The thin layers () provide the dielectric behavior necessary for the capacitor while the antireflective layer () promotes reduced feature sizes by mitigating reflected standing waves, among other things.

Integrated circuit capacitor having antireflective dielectric

The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further include oxidizing the substrate using a wet oxidation process, the wet oxidation process and n-type dopant causing a ratio of oxidation of the implanted region to the unimplanted region to be 2:1 or greater, and then removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region.

Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process

A polysilicon layer ( ) is formed on a dielectric region ( ). An optional metal silicide layer ( ) can be formed on the polysilicon layer. A dielectric layer ( ) is formed over the metal silicide layer and a conductive layer ( ) formed over the dielectric layer. The formed layers are etched by a combination of multi-step dry and wet process to form high precision integrated circuit capacitors.

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Dallas, TX, United States of America

Bill Alan Wofford