Intel Corporation

Bill A Munson

Matthew A North

Ali S Oztaskin

David G Ellis

Leonard W Cross

Balaji Parthasarathy

Andrew T Wilson

Louis J Johnson

Jack W Heller

Lawrence K Freytag

Peter B Bloch

Paul E Greer

Roger L Traylor

John L Allen

Steven R Fordyce

Video data is received from multiple video receptors. This multidimensional video data is converted from the video receptors into a multidimensional audio representation of the multidimensional video data and are the multidimensional audio representation is output using multiple audio output devices. The conversion of the multidimensional video data includes generating a three-dimensional representation of the multidimensional video data, and generating an audio landscape representation with three-dimensional features based on the three-dimensional representation.

Three dimensional audio vision

What is disclosed is a method and apparatus for eliminating the oscillating effect of a light source. The method having the first step of detecting a set of light intensity levels. Then, the method continues by generating a set of pulses based on the set of light intensity levels. The method then determines an oscillating frequency of the light source based upon the set of pulses. The apparatus has a light sensitive diode for detecting a light intensity level from a light source; a level detector coupled to the light sensitive diode for comparing the detected light intensity level with a predetermined level and a pulse generator coupled to the level detector for generating a set of pulses based on an output from the level detector; and, a signal processing unit coupled to the pulse generator to determine an oscillating frequency of the light source.

Method and apparatus for eliminating flicker effects from discharge lamps during digital video capture

A method and apparatus for draining video data from a planarized video buffer in a video camera. The method includes the steps of reading a first sequence of video data from a first plane of the planarized image buffer starting at a buffer address indicated by a first pointer, and then reading a second sequence of video data from a second plane of the planarized image buffer starting at a buffer address indicated by a second read pointer. The apparatus includes an address generation unit and a sequence counter. The address generation unit includes a number of read pointers each configured to indicate a memory location within a different data plane of a video buffer. The address unit is configured to address a sequence of memory locations in a video buffer starting at a location indicated by an active one of the read pointers. The sequence counter is configured to detect when a final memory location of the sequence of memory locations has been addressed by the address generation unit and, in response, to select a different one of the read pointers to be the active read pointer.

Method and apparatus for draining video data from a planarized video

Still image capture under computer control. The computer is instructed to capture the still image capture at an occurrence of a trigger and, subsequently in time, captures the still image. In embodiments, the instructions can be made through a graphical user interface (GUI) displayed on a monitor or a keyboard coupled to the computer. The instruction can start a timed count until the still image is captured. In embodiments the trigger can be an external event, such as sound or motion sensed by appropriate transducers. In yet other embodiments, the computer issues a notification of an occurrence of a capture or a warning of an impending capture.

Still image capture under computer control in response to

A method and apparatus for coupling a video camera to a host computer, e.g., a personal computer, for transmitting video images therebetween. An embodiment of the present invention provides a method and apparatus for delivering video data to a frame buffer in a memory of the host computer wherein the video image may be stored at other than dword aligned memory addresses in the video frame buffer. In an embodiment of the present invention, byte alignment of video data can be controlled according to three categories: 1) adjustment at the start of a video line; 2) adjustment at the end of a video line; and, 3) stride calculation from the end of one line to the beginning of the next line.

Method and apparatus for byte alignment of video data in a memory of a

Method and apparatus for preventing visual artifacts when converting a 24 bits per pixel red-green-blue (RGB) video signal to a 16 bit per pixel video signal, including a decimator circuit for discarding the least significant bits (LSBs) of the red, green and blue color components of a pixel in the RGB video signal. Further included is an error diffusion circuit coupled to the decimator circuit for adding the LSBs of each of the aforementioned color components of a pixel in the RGB video signal to the LSBs of the same color components of a previous pixel in the RGB video signal and factoring a carry generated by the addition into the MSBs of the same color components of a next pixel in the RGB video signal. An edge detector circuit is coupled to the error diffusion circuit for resetting the error diffusion circuit when the MSBs of the color components of the pixel in the RGB video signal are not the same as the MSBs of the color components of the previous pixel in the RGB video stream.

Method and apparatus for eliminating visual artifacts caused by

The present invention provides a direct memory access unit for use in prioritizing the servicing of FIFO buffers in a capture gate array coupled to a video processing device. The capture gate array comprises at least a FIFO input unit having a plurality of FIFO buffers for receiving as input to the capture gate array separated Y, U and V bitmap data entries and a bus interface unit coupled to a video memory bus for outputting the data entries to the video processing device. The direct memory access unit preferably comprises at least a signal generation unit, a logic unit and a control unit. The signal generation unit receives as input from the FIFO unit depth values for the FIFO buffers representing the number of data entries currently stored in respective FIFO buffers in addition to comparators which compare the depth value of each FIFO buffer with at least first and second trip point values stored in at least first and second buffers. The trip point values represent predetermined numbers of data entries within the FIFO buffers, and the second trip point value is set so as to be greater in magnitude than the first trip point value. The signal generation unit then generates a first trip point signal for each FIFO buffer having a depth value equal to or greater than the first trip point value but less than the second trip point value and a second trip point signal for each FIFO buffer having a depth value equal to or greater than the second trip point value. The logic unit is coupled to the signal generation unit and comprises combinational logic for prioritizing the generated trip point signals associated with the respective FIFO buffers. The logic unit further generates FIFO service requests in accordance with the prioritized trip point signals.

Method and apparatus for servicing a plurality of FIFO's in a capture

In an interface connecting a video camera to a host, a method and apparatus for storing video data received from a video camera in video data buffers in the host's memory. The method allows for a large number of video data buffers. Moreover, the video data buffers may be managed by an apparatus other than a processor on the host, thereby offloading the host's processor to perform other tasks. A linked list of commands in memory on the host contain control information, register addresses of registers in the apparatus, and data, which the apparatus utilizes to store received video data in the video data buffers.

Method for storing video data in a plurality of video data buffers on a

An controller for allowing any of a plurality of peripheral devices to dynamically program read and write operations upon a memory. A peripheral device initiates a memory operation by transmitting a plurality of packets of information to the controller which has an interface with the memory. One of the packets includes a read/write bit identifying the memory operation as a read operation or a write operation. Each of the packets is an address packet, a data packet, or a control packet. Each of the packets includes a plurality of packet type bits which identify the type of the packet. The controller has circuitry for decoding and executing the memory operation based on the packet type bits and the read/write bit. A FIFO having a multiplexed input is provided in the controller for storing packets received from the peripheral devices and data read from the memory.

Dynamic programming of bus master channels by intelligent peripheral

A method and apparatus for initializing and determining the topological configuration of a system for processing video information is described. The system has a master device and multiple slave devices for transmitting or receiving video information. The master and slave devices are coupled together in a daisy chain by a serial video link. The master device issues commands to the slave devices to selectively control the routing of a video data stream within each of the slave devices. The master transmits the video data onto the serial video link to the slave devices and assigns a unique address to each of the slave devices based on the responses of the slave devices to the commands and the transmitted data stream. The master device also determines the position in the daisy chain of each of the slave devices based on those responses.

Topological identification and initialization of a system for processing

In a video interface coupling a video camera to a host for displaying a video image from the video camera on a graphics display device coupled to the host, a method for clipping an obscured region of a video image, i.e., a region of the video image covered up on the graphics display device by a window in accordance with a window manager. The video image is clipped prior to being buffered in the graphics memory so that only the portion of the video image that is visible on the graphics display device is actually stored in a buffer in graphics memory. The video interface reads a list in main memory on the host. The list comprises at least one strip descriptor and from 1 to 15 tile descriptors per strip descriptor. A strip descriptor comprises a strip start and a strip end. A tile descriptor comprises a tile start and a tile length. The video interface clips the video image according to the strips and tiles in the clip list. For a given strip, clipping of the video image is performed from the tile start for the tile length specified by a tile descriptor while a scan line of the video image is in the range of a strip descriptor, i.e., between a strip start and a strip end specified by the strip descriptor.

Method and apparatus for source clipping a video image in a video

The camera function of a video conferencing system is enhanced such that it will operate in an automatic adjustment mode for brightness and color for only a predetermined period of time, and only at power up and reset. Once the predetermined period of time has elapsed, the camera function 'locks down' the operating parameters for brightness and color, and switches to a manual adjustment mode. As a result, video image substantially close to the 'ideal image' in brightness and color can be acquired, and yet valuable processor cycles are not wasted in compensating for temporal foreground changes, but instead made available to sustain better frame rates.

Method and apparatus for optimizing camera function for video

An apparatus and method for partitioning video images into a first and second portion for more efficient compression/decompression and transfer across a network is disclosed. The present invention includes a video controller that stores a reference image with a plurality of reference pixels, receives a foreground image, compares the reference image with the foreground image thereby identifying matched pixels, and replaces the matched pixels in the foreground image with null pixels. The video controller also compresses the foreground image, and transfers the foreground image including null pixel values over a network.

Static image background reference for video teleconferencing applications

A circuit for analog chroma keying on color data permits display of graphics, generated from a computer system, and video on an output display. The analog chroma keying circuit receives the graphics signals and the video signals, wherein the graphics signals include color data to designate a color key. The analog chroma keying circuit includes a plurality of digital to analog converters that generate a plurality of color key limits for defining a range to detect the color data denoting the color key. The analog chroma keying circuit also includes a plurality of comparators coupled to receive the graphics signals and the color key limits for each primary color. The plurality of comparators generate a key on indicator when the graphics signals fall within the color key limits. The key on indicator is input to a plurality of analog switches that couples the graphics signals to the output display when the key on indicator indicates the graphics signals are not within the color key limits, and couples the video signals to the output display when the graphics signals are within the color key limits.

Analog chroma keying on color data

A high speed memory interface, contained within a video teleconferencing system, couples a capture first-in first-out (FIFO) device, a host FIFO, a PB FIFO, and a display FIFO to a high speed memory. The interface includes a high speed channel interface, including an arbiter, that allocates bandwidth for the high speed memory for a display service, a capture service, a host service and a refresh service. The capture FIFO receives raw capture video data, buffers the raw capture video data at a capture rate, and transfers the raw capture video data to the high speed memory. The host FIFO receives display video data from a remote source, buffers the display video data, and transfers the input display video data to the high speed memory. The PB FIFO reads capture video data and display video data, during the PB service, from the high speed memory to provide an input queue for video compression and video decompression. The display FIFO receives, during the display service, display video data from the high speed memory, and buffers the display video data to provide the display video data at a display rate for the host. The high speed memory interface has application for use in a computer system supporting video teleconferencing.

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Portland, OR, United States of America

Bill A Munson