Analog Devices,inc.

Infineon Technologies Austria Ag

Analog Devices Global Unlimited Company

Bikiran Goswami

Venkat Sreenivas

Benjamim Tang

Todd Bellefeuille

Baoxing Chen

Kang Peng

Eric C Gaalaas

Richard Pierson

Brian Kirk Jadus

Mark Stewart Cantrell

David R Lewis

Jason J Ziomek

Dongwan Ha

Jason Ma

Felix Qin

An apparatus may include a regulated power converter, a control engine configured to control the regulated power converter based upon a regulation control parameter, a period detection system and a parameter control system. The period detection system may be configured to monitor a signal to detect transient events at an output of the regulated power converter, wherein the transient events include a first transient event and a second transient event after the first transient event. The period detection system may be configured to determine, in response to the second transient event, a transient event period between the first transient event and the second transient event. The period detection system may be configured to determine transient event period information based upon the transient event period. The parameter control system may be configured to set the regulation control parameter to a value determined based upon the transient event period information.

Method and apparatus for period detection-based control of regulation control parameter

An apparatus includes a controller that monitors an error voltage indicating a difference between an output voltage and a setpoint voltage. Based on the monitored error voltage, the controller generates modulation adjustment signals including a frequency adjustment signal and an ON-time adjustment signal. The controller generates a pulse width modulation signal of a first power supply phase in accordance with both the frequency modulation adjustment signal and the ON-time adjustment signal.

Power supply configurations and non-linear control, switching period adjustment and current control based on error signal

An apparatus includes a controller a current mode controller that produces an output voltage by supplying output current from at least one power supply phase of a power supply to power a load. The controller produces an error current signal based on a difference between a magnitude of the output current supplied from the power supply to a load and a phase current setpoint. Based on a magnitude of the error current signal, control a pulse width setting of a pulse width modulation signal controlling the at least one power supply phase. The controller varies a leading edge and a falling edge of a pulse width ON-time of the pulse width modulation signal over each of multiple control cycles depending on variations in the magnitude of the pulse width setting.

Power supply configurations and PWM edge control

An apparatus may include a regulated power converter, a control engine configured to control the regulated power converter based upon a regulation control parameter, and a parameter control system. The parameter control system may be configured to detect a transient event at an output of the regulated power converter. The parameter control system may be configured to modify, in response to the transient event, the regulation control parameter from a first value to a second value based upon a parameter modification profile. The parameter control system may be configured to modify, in response to modifying the regulation control parameter from the first value to the second value, the regulation control parameter according to a function of the parameter modification profile. The function may define a return of the regulation control parameter from the second value to the first value over a period of time.

Method and apparatus for adaptive control of regulation control parameter

Methods and apparatus are disclosed for communicating multiple logic states across a digital isolator. The digital isolator is a universal serial bus (USB) isolator in some embodiments. The digital isolator includes one or more single-bit data channels. Three or more logic states of information are transmitted across the single-bit data channel(s). The logic states are distinguished by a pulse sequence, and in particular a number of edges of the pulse sequence and a final value or final edge of the pulse sequence.

Coding schemes for communicating multiple logic states through a digital isolator

An apparatus includes a controller that monitors an error voltage indicating a difference between an output voltage and a setpoint voltage. Based on the monitored error voltage, the controller generates modulation adjustment signals including a frequency adjustment signal and an ON-time adjustment signal. The controller modulates a pulse width modulation signal of a first power supply phase in accordance with both the frequency modulation adjustment signal and the ON-time adjustment signal.

Multi-dimensional pulse width modulation control

An embodiment of a communication circuit for communicating data across an isolation barrier may include an input circuit to receive a plurality of input data channels, a framing circuit to frame an input data packet from the plurality of input data channels, an encoding circuit to select a characteristic of a data symbol to represent a plurality of bits of the framed input data packet, and a driver circuit to drive one or more data symbols representing the framed input data packet onto an isolator configured to communicate data across the isolation barrier. The encoding circuit may select an amplitude, frequency or phase of the data symbol from a plurality of predetermined amplitudes, frequencies or phases, to encode the plurality of bits as the selected amplitude, frequency or phase. The communication circuit also may include a receive circuit to receive one or more second data symbols from the isolator, a decoding circuit to decode a plurality of bits of an output data packet as a function of a characteristic of the second data symbol, and a deframing circuit to deframe the output data packet into output data of a plurality of output data channels.

Circuits and systems for multiplexed isolator communication

A device for providing a reset signal to one or more sequential logic circuits in an electronic system responsive to a supply voltage condition includes a first voltage detector circuit to generate a first pulse after the supply voltage rises to a first threshold voltage level. The device further includes a second voltage detector circuit to generate a second pulse after the supply voltage falls below a second threshold voltage level. The device additionally includes a latch circuit to store a first value based on the first pulse after the supply voltage rises to the first threshold voltage level, disable the first voltage detector circuit after storing the first value, reset to store a second value based on the second pulse after the supply voltage falls below the second threshold voltage level, and to disable the second voltage detector circuit after the resetting.

Low quiescent current power on reset circuit

An embodiment of a communication system for transmitting and receiving data across an isolation barrier may include a communication circuit connected to an isolator at a first side of the isolation barrier, the communication circuit having a transmit circuit to drive a first data signal onto the isolator based on input data received by the communication circuit, a receive circuit to receive a second data signal from the isolator and produce output data based on the received second data signal, and a control circuit to control the transmit and receive circuits to provide time division multiplexing of the first and second data signals. The control circuit may transition to a transmit state in which the transmit circuit drives the first data signal onto the isolator from a receive state in which the receive circuit receives the second data signal from the isolator in response to detecting a condition as a function of receiving a predetermined number of bits of the second data signal and passage of a predetermined time period.

A system may include a plurality of isolators to transfer data signals across an isolation barrier, one of the signals including a clock signal. A delay circuit may be included to receive the clock signal and provide a delayed clock signal that lags the clock signal by an amount representing a delay across the isolation barrier. The delayed clock signal may be delayed by a round trip propagation delay over the isolation barrier. The delayed clock signal may be used as a reference to read data sent over the isolation barrier.

Integrated delayed clock for high speed isolated SPI communication

A multi-channel isolation system has N+1 isolators for N channels of communication data. N of the isolators may transfer data signals across an isolation barrier, one for each of the N channels of data. An N+1isolator transfers refresh signals representing state of the data signals on the N isolators. Receiver circuitry, therefore, may receive signals from the N isolation channels without risk for collision with refresh signals. If reception of the refresh signals becomes necessary, circuitry on a receive side of the isolator may switch over to the N+1receive path to output state data contained in the refresh signals.

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Burlington, MA, United States of America

Bikiran Goswami