Intel Corporation

Biju Puther Simon

Tessil Thomas

Ajay Harikumar

Supratim Pal

Namita Sharma

Tovinakere D Vivek

Kiran Singh Panesar

An apparatus to facilitate matrix processing is disclosed. The apparatus comprises a matrix accelerator to receive input matrix data, transform the input matrix data into a plurality of sub-blocks, examine a first block of the sub-blocks to determine whether the first block comprises sparse data, select a first tile size upon a determination that the first block comprises sparse data and generate output matrix data based on the first tile size.

Sparse matrix optimization mechanism

In one aspect, the issues of events that may impact one or more partitions of sub-socket partitioning in one or more sockets can be handled. Specifically, events for partitions can be handled in a socket with sub-socket partitioning, wherein the events may include reset, interrupts, errors and reliability, availability, and serviceability (RAS) management.

Method, system and apparatus for handling events for partitions in a socket with sub-socket partitioning

Embodiments enable sub-socket partitioning that facilitates access among a plurality of partitions to a shared resource. A round robin arbitration policy is to allow each partition, within a socket, that may utilize a different operating system, access to the shared resource based at least in part on whether an assigned bandwidth parameter for each partition is consumed. Embodiments may further include support for virtual channels.

Method, system and apparatus for main memory access subsystem usage to different partitions in a socket with sub-socket partitioning

A cache that supports sub-socket partitioning is discussed. Specifically, the cache supports different quality of service levels and victim cache line selection for a cache miss operation. The different quality of service levels allow for programmable ceiling usage and floor usage thresholds that allow for different techniques for victim cache line selection.

Method, apparatus, and system for shared cache usage to different partitions in a socket with sub-socket partitioning

Sub-socket partitioning is enabled using embodiments of the present invention. In one aspect, the memory mapping is performed to isolate memory access for each of the partitions by assigning a partition address and a generated physical address.

Method, system and apparatus for memory address mapping for sub-socket partitioning

A method of booting up a computer system comprising a first multi-cored processor comprising a first plurality of cores and a second multi-cored processor comprising a second plurality of cores is disclosed. The method may comprise configuring a first partition comprising a first one or more cores from the first plurality of cores and from the second plurality of cores, configuring a second partition comprising a second one or more cores from the first plurality of cores and from the second plurality of cores, and configuring a third partition comprising a third one or more cores from the first plurality of cores and one or more cores from the second plurality of cores.

Growing community of inventors

Bengaluru, India

Biju Puther Simon