Koninklijke Philips Corporation N.v.

Nxp B.v.

St-ericsson Sa

Bijo Thomas

Milind Manohar Kulkarni

Sainath Karlapalem

Nagaraju Bussa

Biju Ravindran

A vehicle parking assistance system is based on presenting a bird's eye view. The display has an input interface such as a touch-input display or a remote input device such as a joystick. In this case, by selecting a desired position on the display (which is presenting an image of an object or location in space for which the driver is wanting to know the range), the user is able to request a distance calculation between the vehicle and that location in space. The distance information can be provided as an audible message and/or as a visual overlay message onto the bird's eye view.

Parking assistance system and method

A data processing system is provided with at least one processing unit () for an interleaved processing of multiple tasks (T-T), and a cache () associated to the at least one processing unit () for caching data for the multiple tasks (T-T) to be processed by the at least one processing unit (). The cache () is divided into a plurality of cache lines (). Each of the cache lines () is associated to one of the multiple tasks (T-T). Furthermore, a task scheduler () is provided for scheduling the multiple tasks (T-T) to be processed in an interleaved manner by the at least one processing unit (). A cache controller () is provided for selecting those cache lines () in the cache (), which are to be evicted from the cache (). This selection is performed based on the task scheduling of the task scheduler ().

Data processing system and method for cache replacement using task scheduler

A method and system for bus arbitration to be used in a system having a plurality of data handling units () and a shared bus () with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.

Method and system for bus arbitration

A data processing system includes processing units for processing data, at least one memory for storing data from the processing units, an interconnect for connecting the processing units and the memory. The processing units request write access to the memory via the interconnect to write data into the memory. At least one arbiter performs interconnect arbitration for the access to the memory from the processing units, wherein interconnect arbitration is performed based on the minimum logic level changes of the interconnect as introduced by the write accesses of the processing units to the memory. If more than one write request is available from different processing units the interconnect arbitration (interconnect access), is granted to that processing unit, whose data to be sent to the memory via the interconnect results in minimum logic level changes to the interconnect. Power dissipation due to switching of logic levels is reduced.

Data processing system and method for interconnect arbitration

A data processing system is provided comprising at least one processing unit for processing data; a memory means for storing data; and a cache memory means for caching data stored in the memory means. Said cache memory means is associated to at least one processing unit. An interconnect means is provided for connecting the memory means and the cache memory means. The cache memory means is adapted for performing a cache replacement based on reduced logic level changes of the interconnect means as introduced by a data transfer between the memory means and the cache memory means.

Data processing system and method of cache replacement

An electronic data processing circuit contains a plurality of data handling units (a-d,a-b) with data outputs, at least part of the data handling units having address outputs. The data handling units supply words of preferably selectable size to a bus. A bus controller () is arranged to control access to the bus in successive access cycles. The bus controller () causes data bits from a plurality of data words from respective ones of the data handling units (a-d,a-b), to be placed in combination on the data lines in a same bus cycle. The bus controller causes write addresses that the respective ones of the data handling units (a-d,a-b) supply for respective ones of the plurality of data words to be placed on the address lines in a plurality of respective bus cycles. Preferably, the temporal or spatial arrangement of the data words on the bus lines adapted so as to minimize the number of logic level changes on the bus.

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Kottayam, India

Bijo Thomas