Lucent Technologies Inc.

Pmc-sierra, Inc.

Texas Instruments Corporation

Bijit Thakorbhai Patel

Bernard Lee Morris

Makeshwar Kothandaraman

Wayne E Werner

Thaddeus John Gabara

Marius Moe

Tarjei Aaberge

Graeme Barclay Boyd

David Arthur Rich

Carol Ann Huber

Xun Cheng

Joseph David Coyne

Chao Xu

Michael Shinkarovsky

Clifford B Cole

Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.

Gated ring oscillator linearization

A negative electrostatic discharge (ESD) protection network or circuit is described. The circuit can provide protection against a negative-going ESD transient. One embodiment, along with standard positive ESD protection networks, can discharge ESD currents in both polarities and is able to tolerate a positive/negative voltage that is higher than the maximum voltage allowed for the given fabrication process. It can be used to protect an I/O pin that can be exposed to a relatively wide signal swing range.

Systems and methods for ESD protection

An architecture is provided for implementing bypass, repeater and retimer functions in high-speed multi-port SERDES bypass ports and devices. Specifically, this architecture uses clock recovery to implement a repeater function which retransmits data synchronously at a recovered-clock rate, providing very low-latency as no elastic-buffers are required to perform clock-rate compensation. It also supports a full retiming function where incoming data is retransmitted synchronously to the local-clock domain, in which case elastic-buffers are needed to compensate for differences between incoming clock and local-clock domains. The architecture disclosed herein is advantageously used for Fibre-Channel Arbitrated Loop (FCAL) applications. It can also be leveraged in other applications like Infiniband, XAUI, PCI-Express to create a single device that be used as 'eye-opener' to extend reach with low-latency when operated in 'repeater mode' and as retiming device when operated as &#x201c;retimer-mode&#x201d;. It can also perform as an amplifier with very low-latency when operated in bypass-mode.

Multi-function bypass port and port bypass circuit

VCO frequency is continuously variable through a wide frequency range in proportion to a first control voltage VC produced by a PLL containing the VCO. A second control voltage NVC is produced as a monotonically decreasing function of VC. A first current I is produced in proportion to VC and a second current I is produced in proportion to NVC. I is subtracted from I , producing a control current IC&equals;I -I which is applied to the VCO.

Extended frequency range voltage-controlled oscillator

A differential receiver having a precision input referred offset and a wide CMR, wherein a pair of differential-difference amplifiers are used as differential comparators. The differential-difference amplifiers are configured to allow a precision input-referred offset to be set by the use of two reference voltages. The differential comparators each have a common-mode range over a different portion of the rail-to-rail voltage range. A first one of these differential comparators is activated when the input common-mode voltage is above a threshold level. A second differential comparator is activated when the input common-mode voltage is below the threshold. The output of the differential comparator that is selected is to provide a comparison output signal, thereby achieving a wide CMR. The selection of either the first or second differential comparator is made by a selection circuit that includes a differential Schmitt Trigger and a multiplexer.

Wide common-mode differential receiver with precision input referred

Embodiments of the invention include an amplifier such as a differential amplifier having an improved common mode voltage range (CMVR). The amplifier includes a translator coupled to a second stage amplifying circuitry wherein the translator uses feedback and a parallel connection of input devices to improve the common mode voltage range of the amplifier while providing for enablement of the circuit functionality. The translator uses parallel connections of N-channel and P-channel devices such as transistors to extract alternating current (ac) signals riding on a common mode voltage and to translate the extracted ac signals to ride on a constant reference voltage (V.sub.ref). The translated signals are then amplified in a conventional manner, such as by a gate thresholding or a self-biasing technique. An input sensing circuit within the translator provides an offset detection signal to a correction circuit, also within the translator. The correction circuit compares the signal with an applied reference signal (V.sub.ref) and, based thereon, applies a correction signal to the input sensing circuit. With the benefit of such correction signals, the input sensing circuit translates an input signal with a large common mode voltage range to an output signal that rides on the dc voltage that is approximately equal to the reference signal, V.sub.ref.

Amplifier having improved common mode voltage range

An integrated circuit has digital logic that supports two or more different processing speeds and two or more different data rates that are distinguished by each data rate having a data prefix at a different common-mode voltage. For normal processing, the integrated circuit has one or more comparators that compare the average signal voltage level with one or more reference voltages to determine the data rate. According to one embodiment of the invention, one or more muxes are configured between the comparators and the digital logic. These muxes can be controlled during testing to by-pass the operations of the comparators to pass specified digital codes to the digital logic to simulate the operations of the comparators. In this way, the different processing speeds of the digital logic can be tested without having to build special automatic test equipment to support all of the different possible voltage levels corresponding to the different supported data rates.

Speed-signaling testing for integrated circuits

CMOS technology is used to create a controlled output impedance output buffer circuit. An output buffer driver uses buffer circuits having impedance elements with linear characteristics. A control circuit uses a known impedance load to control the impedance of the buffer circuits. The control circuit monitors a known current flowing through the known impedance load to determine whether the output buffer circuit's output impedance needs to be adjusted to match a transmission line's impedance. Adjustments occur when the control circuit generates control signals to turn on or off various buffer circuits (and their impedance elements) contained within the output driver. In doing so, the output buffer circuit ensures that its output impedance will match the impedance of a transmission line over the entire range of output voltages regardless of the variations caused by the manufacturing process, operation temperature and power supply voltage.

Controlled output impedance buffer using CMOS technology

A low voltage CMOS input buffer protection circuit that is used to protect an input buffer from any high voltage signal (e.g., 5 V) that may appear along a signal bus. The protection circuit is also 'hot-pluggable', meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). The circuit includes a CMOS transmission gate and utilizes on-chip generated reference voltages to provide the necessary protection.

CMOS input buffer protection circuit

A CMOS high voltage drive output buffer that protects the drive stage from seeing relatively high voltages (e.g., 5 V) during 'hot pluggable' conditions (that is, when the reference voltage VDD is not present). A transmission gate and clamping transistors are disposed around the output devices to provide the requisite protection. A backgate bias generator for use with P-channel devices is also disclosed that is capable of withstanding 'hot pluggable' conditions.

CMOS high voltage drive output buffer

An integrated, low power bus holder circuit implemented in low voltage technology is capable of interfacing with a relatively high voltage bus. In an illustrative embodiment, the bus holder circuit includes a first inverter for inverting a logic voltage present on a data bus and a second inverter for inverting the output of the first inverter. The second inverter is comprised of a series string of first and second pFETS and first and second nFETS, with the gates of the first pFET and first nFET coupled to the output of the first inverter. The data bus is coupled to a first circuit node between the second nFET and second pFET, and the bus logic level is maintained thereat. A third pFET is coupled to the second inverter and conducts current when a high logic voltage is present on the bus. A resistance device is coupled between a drain of the third pFET and a point of low reference potential. Advantageously, the circuit arrangement of the illustrative embodiment does not draw any DC power since it avoids the use of a separate, DC power consuming biasing circuit to bias the third pFET. A fourth pFET is preferably employed to eliminate leakage current in the first inverter.

Low power, high voltage-tolerant bus holder circuit in low voltage

A current output circuit comprises a current driver that is switchably connected across two output nodes by a switching assembly and having a switchable shunt resistor connected across the current driver. The switchable shunt resistor may be switched between a non-conducting state and a resistive conducting state. In a first data state, the current driver is connected to the output nodes by the switching assembly and the switchable shunt resistor is non-conducting so that the supplied current will flow through a load attached to the output nodes. In a second data state, the current driver is disconnected from the output nodes and the switchable shunt resistor is in a resistive conducting state. In this state the current bypasses the load and is diverted through the switchable shunt resistor. Several current drivers with appropriate switching arrangements and one or more switchable shunt resistors may be provided to allow for asymmetric current outputs in various data states.

Current steering output circuit with switchable shunt resistor

A CMOS voltage generator for providing a reference voltage VDD2 that will track the low level power supply voltage VDD (approximately 3.0V-3.6V) as long as the power supply is present. When VDD is not present (defined as at 'hot pluggable' condition), the voltage generator is configured to maintain a 'protection' output voltage less than the relatively high voltage (approximately 5V) that may appear along a circuit signal bus. In particular, the circuit includes at least a pair of diode-connected N-channel devices disposed between the signal bus line and the output voltage terminal to provide the necessary protection.

CMOS reference voltage generator

A low voltage CMOS output buffer protection circuit is configured to protect an associated output buffer from any high voltage signals (e.g., 5V) that may appear along a signal bus line. The protection circuit is also 'hot-pluggable', meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). An on-chip reference voltage generator is used to provide a reference voltage VDD2 that will be essentially equal to VDD as long as VDD is present. When VDD is not present, VDD2 will track the signal appearing along the signal bus (PAD), remaining at least two diode drops below the PAD voltage.

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Breinigsville, PA, United States of America

Bijit Thakorbhai Patel