International Business Machines Corporation

Bijian Chen

Yaoguang Wei

Stephen Thomas Quay

Ying Zhou

David James Hathaway

Kerim Kalafala

Alexander Joel Suess

Nathaniel Douglas Hieter

Amanda Christine Venton

Eric Chien Lai

Jeffrey S Piaget

Peter Milton Nasveschuk

Embodiments of the invention include protecting against antenna violations in a macro having a clock mesh. Aspects include obtaining a design of the macro, the design including a clock layer having a plurality of clock pins and determining a longest vertical wire and a longest horizontal wire allowed based on a design of the clock mesh. Aspects also include identifying, based at least in part on the longest vertical wire and the longest horizontal wire, a plurality of checkbox regions for a clock pin of the plurality of clock pins and calculating a total diffusion area for each of the plurality of checkbox regions. Aspects further include adding, to the design of the macro, an antenna diode to the clock pin based on a determination that the total diffusion area for any of the plurality of checkbox regions is less than a threshold value.

Predictive antenna diode insertion in a macro having a clock mesh

A method a system include obtaining a master list of layer traits including wire codes, each of the wire codes indicating a width of a corresponding wire, and including a maximum reach length of the corresponding wire and a time of flight (TOF) through the corresponding wire. The method also includes processing the master list of the layer traits to obtain a final list of the layer traits, the final list of the layer traits having fewer entries than the master list of the layer traits and being in a ranked order. A metric is calculated for each adjacent pair of the layer traits in the final list of layer traits. The final list of the layer traits and the corresponding metric is used to assign the corresponding wires to different interconnects among components of an integrated circuit.

Automatic layer trait generation and promotion cost computation

Methods and systems for improving the performance of a computer performing an electronic design. One or more nets of a netlist are sorted based on an amount of slack and a net of the one or more nets that is unprocessed and that has a least amount of slack is selected as a current target net. A layer of a higher bucket that is unprocessed for the currently selected target net is selected, the higher bucket being higher than a bucket of the current target net. A determination of whether capacity is available to route the current target net on the selected layer of the higher bucket is made and the current target net is routed on the selected layer of the higher bucket in response to capacity being available. One or more nets that are competing for resources with the current target net on the selected layer of the higher bucket are identified as candidate nets in response to capacity not being available.

Net layer promotion with swap capability in electronic design

Managing virtual boundaries to enable lock-free concurrent region optimization, including: receiving a model of an integrated circuit ('IC'); dividing the model into a plurality of regions, wherein none of the plurality of regions overlap with another region; assigning each of the plurality of regions to a thread of execution, wherein each thread of execution utilizes a shared memory space; and optimizing, by each thread in parallel, the assigned region.

Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit

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Austin, TX, United States of America

Bijian Chen