Intel Corporation

Biji George

Sreenivas Subramoney

Dipan Kumar Mandal

Om Ji Omer

Yuval Amizur

Leor Banin

Belliappa Manavattira Kuttanna

Lance E Hacking

Nir Dvorecki

Cormac Brick

Shengbo Xu

Gurpreet Singh Kalsi

Chulong Chen

Saiveena Kesaraju

Gopi Neela

Pradyumna S Singh

Wenling Margaret Huang

Ivan Simões Gaspar

Hao Chen

According to various embodiments, a radar device is described comprising a processor configured to generate a scene comprising an object based on a plurality of receive wireless signals, generate a ground truth object parameter of the object and generate a dataset representative of the scene and a radar detector configured to determine an object parameter of the object using a machine learning algorithm and the dataset, determine an error value of the machine learning algorithm using a cost function, the object parameter, and the ground truth object parameter and adjust the machine learning algorithm values to reduce the error value.

High end imaging radar

A disclosed apparatus to multiply matrices includes a compute engine. The compute engine includes multipliers in a two dimensional array that has a plurality of array locations defined by columns and rows. The apparatus also includes a plurality of adders in columns. A broadcast interconnect between a cache and the multipliers broadcasts a first set of operand data elements to multipliers in the rows of the array. A unicast interconnect unicasts a second set of operands between a data buffer and the multipliers. The multipliers multiply the operands to generate a plurality of outputs, and the adders add the outputs generated by the multipliers.

Methods, apparatus, articles of manufacture to perform accelerated matrix multiplication

One embodiment provides an image processing circuitry. The image processing circuitry includes a feature extraction circuitry and an optimization circuitry. The feature extraction circuitry is to determine a feature descriptor based, at least in part, on a feature point location and a corresponding scale. The optimization circuitry is to optimize an operation of the feature extraction circuitry. Each optimization is to at least one of accelerate the operation of the feature extraction circuitry, reduce a power consumption of the feature extraction circuitry and/or reduce a system memory bandwidth used by the feature extraction circuitry.

Optimized image feature extraction

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Bengaluru, India

Biji George