Freescale Semiconductor,inc.

Motorola Corporation

Soitec

S.o.i.tec Silicon on Insulator Technologies

Other

National University of Singapore

Peregrine Semiconductor Corporation

Bich-Yen Nguyen

Mariam G Sadaka

Voon-Yew Thean

Ted R White

Da Zhang

Carlos Mazure

Alexander L Barr

Philip J Tobin

Richard Ferrant

Marius K Orlowski

Christophe Maleville

James D Hayden

Leo Mathew

Sucharita Madhukar

Olubunmi O Adetutu

Walter Schwarzenbach

Shawn George Thomas

Bernard J Roman

Victor H Vartanian

Brian J Goolsby

Chun-Li Liu

Tab Allen Stephens

Kent J Cooper

Vidya S Kaushik

Ramachandran Muralidhar

David L O'Meara

Alexander Barr

Scott S Roth

Venkat Kolagunta

Nicolas Daval

Ludovic Ecarnot

Michael P Woo

Konstantin Bourdelle

Dina H Triyoso

Dejan Jovanovic

Wayne J Ray

Jian Feng Chen

Sufi Zafar

Chitra K Subramanian

Michael Alan Sadd

Ionut Radu

Howard C Kirsch

Carlos A Mazure

James Kenyon Schaeffer, Iii

Richard D Sivan

Zhonghai Shi

Yeong-Jyh Tom Lii

John M Grant

Jung-Hui Lin

Thomas F McNelly

Prasad Venkatraman

Wei E Wu

James R Pfiester

James David Burnett

Sinan Goktepeli

Prashant U Kenkare

Brian A Winstead

William James Taylor, Jr

Israel A Lesk

Paul T Lin

Kimberly Gay Reid

Nadia Ben Mohamed

Paul Grudowski

Alain Duvallet

Zhiyi Jimmy Yu

Bruce E White

Kurt W Eisenbeiser

Louis C Parrillo

Daniel Delprat

Cécile Aulnette

Bikas Maiti

Christophe Figuet

Gweltaz Gaudin

Jeffrey Pearse

Thien T Nguyen

Gregory S Spencer

Karl L Wang

Christopher C Hobbs

Omar Zia

Shih-Wei Sun

Sergio A Ajuria

Rode R Mora

Vance H Adams

Frederic Allibert

Wayne M Paulson

Yong Liang

Scott Daniel Hector

John R Alvis

Alexander A Demkov

Yang Du

Marc A Rossow

Jeffrey M Finder

Kuntal Joardar

Stefan Zollner

Matthew W Stoker

Jonathan L Cobb

Percy V Gilbert

Anthony Mark Miscione

Veeraraghavan Dhandapani

Keith G Kamekona

A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about −0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon-on-insulator device.

Device architectures with tensile and compressive strained substrates

A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.

Method for manufacturing a CFET device

A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400&#xb0; C. and a semiconductor layer extending on the first substrate comprises:

Method for manufacturing a structure for forming a tridimensional monolithic integrated circuit

A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.

Method for manufacturing a semiconductor structure

A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer; assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.

Method for fabrication of a semiconductor structure including an interposer free from any through via

A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor layer over a high-resistivity substrate, such that the dielectric layer is arranged between the high-resistivity substrate and the semiconductor layer; b) forming a hard mask or resist over the semiconductor layer, wherein the hard mask or resist has at least one opening at a predetermined position; c) forming at least one doped region in the high-resistivity substrate by ion implantation of an impurity element through the at least one opening of the hard mask or resist, the semiconductor layer and the dielectric layer; d) removing the hard mask or resist; and e) forming a radiofrequency (RF) circuit in and/or on the semiconductor layer at least partially overlapping the at least one doped region in the high-resistivity substrate.

Method for manufacturing a high-resistivity semiconductor-on-insulator substrate including an RF circuit overlapping a doped region in the substrate

The invention relates to a structure for radiofrequency applications comprising: a monocrystalline substrate, a polycrystalline silicon layer directly on the monocrystalline substrate, and an active layer on the polycrystalline silicon layer intended to receive radiofrequency components. At least a first portion of the polycrystalline silicon layer extending from an interface of the polycrystalline silicon layer with the monocrystalline substrate layer includes carbon and/or nitrogen atoms located at the grain boundaries of the polycrystalline silicon layer at a concentration of between 2% and 20%. A process for manufacturing such a structure includes, during deposition of at least a first portion of such a polycrystalline silicon layer located at the interface with the monocrystalline substrate, depositing carbon and/or atoms in the at least a first portion.

Structure for radiofrequency applications and process for manufacturing such a structure

Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures

Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers

The invention relates to a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G, G) and a second (G, G) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G, G).

Pseudo-inverter circuit with multiple independent gate transistors

Three-dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling a waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.

Methods of forming three-dimensionally integrated semiconductor systems including photoactive devices and semiconductor-on-insulator substrates

The present disclosure relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The disclosure also relates to the wafer that is produced by the new method.

Wafer with intrinsic semiconductor layer

Growing community of inventors

Austin, TX, United States of America

Bich-Yen Nguyen