Intel Corporation

Other

Bibiche M Geuskens

Vivek K De

Muhammad M Khellah

Jaydeep P Kulkarni

James W Tschanz

Tanay Karnik

Arijit Raychowdhury

Muhammed M Khellah

Christopher B Wilkerson

Alaa R Alameldeen

Gunjan H Pandya

Eric Kwesi Donkoh

Ataur Patwary

Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks

Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.

Apparatus for reducing write minimum supply voltage for memory

Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a processor). Other embodiments are also described.

Reducing minimum operating voltage through hybrid cache design

In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.

Memory write operation methods and circuits

Provided herein is a new RF implementation. Instead of using a pre-charged High node for one or more of its evaluation nodes, it employs an evaluation (or evaluate) node that is discharged (Low) prior to evaluation and enters evaluation in a discharged state. In some embodiments, with such 'normally Low' evaluation nodes, it uses pull-up stack devices, rather than pull-down devices, to charge the evaluate node during an evaluate phase if the logic so dictates.

Register file circuits with P-type evaluation

A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write operations of the memory array. By doing so, the NMOS devices in the memory array are strengthened and the contention between the NMOS and PMOS devices are reduced during read and/or write operations of the memory array. This helps to lower or reduce the required VCCof the memory array during read and/or write operations of the memory array.

Growing community of inventors

Beaverton, OR, United States of America

Bibiche M Geuskens