Broadcom Corporation

Bibhudatta Sahoo

Morteza Cyrus Afghahi

Esin Terzioglu

Gil I Winograd

Ali Anvar

Andrew Chen

According to one exemplary embodiment, a memory cell in a semiconductor chip includes a non-volatile memory transistor, a control gate, and a floating gate. The control gate is capacitively coupled to the floating gate of the non-volatile memory transistor by a metal capacitor. The metal capacitor can be formed in one or more metal levels and in one embodiment is in a shape of a comb with multiple fingers. In one embodiment, the non-volatile memory transistor is an NMOS non-volatile memory transistor.

Non-volatile memory cell with metal capacitor

The present invention relates to a system and method for equalizing the capacitance between/among n lines of a bus running in parallel for a portion of their length. The system and method include determining a twisting pattern for the n lines using an algorithm for example. After determining the twisting pattern forming at least n&#x2212;1 twisted sections, the n lines are twisted according to the pattern so that each of the n lines runs along every other line for a same distance across the length of a bus.

Bus twisting scheme for distributed coupling and low power

A content addressable memory cell () includes a circuit () operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first point () and a second bit of complementary data at a second point (). A first transistor () comprising a first gate () is switchable to first and second states in response to predetermined relationships between the first and second bits and third and fourth test bits transmitted on first and second lines (and). Second and third transistors () comprise gates () coupled to the first line () and second line () and comprise circuit paths () coupling the first and second points to the first gate.

Content addressable memory cell techniques

The present invention relates to a system and method for equalizing the capacitance between at least two lines of a bus running in parallel for a portion of their length. The system and method include determining a twisting pattern for the lines using an algorithm. After determining the twisting pattern, the lines are twisted according to the pattern so that each of the lines runs along every other line for a same distance across the length of the bus.

A content addressable memory cell ( ) includes a circuit ( ) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first point ( ) and a second bit of complementary data at a second point ( ). A first transistor ( ) comprising a first gate ( ) is switchable to first and second states in response to predetermined relationships between the first and second bits and third and fourth test bits transmitted on first and second lines ( and ). Second and third transistors ( ) comprise gates ( ) coupled to the first line ( ) and second line ( ) and comprise circuit paths ( ) coupling the first and second points to the first gate.

Growing community of inventors

Tustin, CA, United States of America

Bibhudatta Sahoo