Ablic Inc.

Other

Seiko Instruments Inc

Abli Inc.

Tianjin Lishen Battery Co., Ltd.

Biao Shen

Toshiyuki Tanaka

Eiki Imaizumi

Hiroyuki Yonetani

Kazuhisa Suzuki

Toshiyuki Uchida

A serial communication interface device includes a converter, a transmitter, and a receiver. The converter generates a first signal and a second signal based on changes in a clock signal, and a third signal and a fourth signal based on changes in a data signal, converts into the clock signal and the data signal based on the first to the fourth signals, sets the transmission start signal in response to receiving the fourth signal during a period where the clock signal is a first level, and sets the transmission end signal in response to reception of the third signal after reception of the first signal. The transmitter converts the first to the fourth signals into a communication signal and transmits the communication signal to a communication line. The receiver converts the communication signal received from the communication line into the first to the fourth signals.

Serial communication interface device

A battery voltage monitoring device includes a clock generation circuit; a switch circuit including first and second N-type transistors and first and second P-type transistors of which sources and back gates are connected to each other, with a drain of one of the first N-type transistor and the first P-type transistor connected to the other source, one source connected to a signal input unit, and the other drain connected to a signal output unit, and a source of one of the second N-type transistor and the second P-type transistor connected to the other source, one source connected to a signal input unit, and the other drain connected to a signal output unit; a first generation circuit generating first and second control signals for the first and second P-type transistors, respectively; and a second generation circuit generating third and fourth control signals for the first and second N-type transistors, respectively.

Battery voltage monitoring device

The present invention provides a ΔΣ AD converter and a sensor device having a small circuit scale and high conversion accuracy. A ΔΣ AD converter includes a ΔΣ AD modulator, an accumulator, a counter, an adjustment value storage part, a first adder, a cumulative value latch part, and a control circuit. The control circuit outputs to the adjustment value storage part a signal designating a temperature range according to the adjustment cumulative value received from the first adder in a case where the count value received from the counter reaches a predetermined value. The adjustment value storage part outputs the adjustment value of the offset value and the adjustment value of the count value according to the signal to the first adder and the counter. The control circuit outputs the latch signal to the cumulative value latch part in response to completion of counting by the counter.

Δ-Σ AD converter and sensor device

A bus arbitration circuit includes a first bus port, a second bus port, a first output circuit connected to the first bus port, a second output circuit connected to the second bus port, a control circuit, and a switch circuit. The control circuit includes a first input port, a second input port, a control signal output port, and an output port. The first input port receives data of the first bus port, the second input port receives data of the second bus port, and data is outputted from the output port to an input port of the first output circuit. The switch circuit has an input port connected to the first bus port, a control port connected to the control signal output port of the control circuit, and an output port from which data of a host bus is outputted to an input port of the second output circuit.

Bus arbitration circuit and data transfer system including the same

The battery protection integrated circuit includes: a higher-level reception terminal configured to receive information from a higher-level circuit; a lower-level transmission terminal configured to transmit information to a lower-level circuit; a storage configured to store a unique identification information; a higher-level signal input terminal configured to be supplied with a permission signal; a lower-level signal output terminal configured to output a second permission signal to the lower-level circuit; a storage controller configured to store a unique identification information when the identification information is not stored, and when the permission signal is supplied; and a switch configured to make the lower-level signal output terminal not provide the second permission signal when the identification information is not stored in the storage, and make the lower-level signal output terminal provide the second permission signal when the identification information is stored in the storage.

Battery protection integrated circuit and battery management system

A battery protection integrated circuit which is used to construct a system configured to serially communicate among a plurality of the battery protection integrated circuits, the battery protection integrated circuit includes: a higher-level transmission terminal; a lower-level reception terminal; an acquisition device configured to acquire transmission information to transmit to the higher-level circuit; and a storage configured to store at least one of transmitted information transmitted from the lower-level circuit and the transmission information acquired by the acquisition device, the battery protection IC being configured to transmit, in response to reception of instructive information indicating an instruction for the higher-level circuit to read the transmitted information, one of the transmitted information and the transmission information from the higher-level transmission terminal to the higher-level circuit, and simultaneously receive, by the lower-level reception terminal, transmitted information transmitted from the lower-level circuit after the transmitted information.

Provided is a relaxation oscillator having an extremely small temperature deviation in oscillation frequency. A first current (I) generated by a reference voltage source and a first resistor having a positive first-order temperature coefficient is supplied to a first variable capacitor (C) for oscillation, and a second current (I) generated by a reference voltage source and a second resistor having a negative first-order temperature coefficient is supplied to a second variable capacitor (C) for oscillation. A product of a value of a ratio of a first current to a second current and a value of a ratio of a first-order temperature coefficient of the second resistor to a first-order temperature coefficient of the first resistor, and a value of a ratio of a capacitance of the first variable capacitor to a capacitance of the second variable capacitor have the same absolute value and opposite signs.

Relaxation oscillator and wireless device including relaxation oscillator

To provide a semiconductor device capable of easily testing a built-in self-test control circuit itself, the semiconductor device has: a test pattern generator; an output response analyzer configured to compare an expected value to a test result of a circuit; a plurality of test control circuits each configured to control the test pattern generator and the output response analyzer; and a circuit under test. The semiconductor device has: a first test mode in which a first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test; and a second test mode in which the test control circuit other than the first test control circuit controls the test pattern generator and the output response analyzer to cause the test pattern, to thereby perform a test.

Semiconductor device

Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data, the memory device being built from an OTP memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the memory sets operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block.

Memory device and memory access method

Provided is a memory device in which the circuit structure is simplified while the functions of a memory including an OTP memory and a memory including a pseudo-MTP memory are maintained. A memory device includes a plurality of memory sets each including a mark bit storage area for storing a mark bit, which indicates that an object is deleted data, and a data bit storage area for storing data to be stored, the memory device being built from a one time programmable (OTP) memory including an OTP memory block and a pseudo-MTP memory block, the OTP memory block containing a given number of memory sets selected out of the plurality of memory sets to operate as an OTP memory, the pseudo-MTP memory block containing the rest of the plurality of memory sets which remains after the memory sets of the OTP memory block are excluded and operates as a pseudo-MTP memory. The mark bit is written in advance in the mark bit storage area of the OTP memory block.

Growing community of inventors

Chiba, Japan

Biao Shen