Samsung Electronics Co., Ltd.

Bi-woong Chung

Nam-Shik Kim

Dae-Wook Kim

Jun-Jin Kong

A method of performing a cyclic redundancy check (CRC) operation in a memory system, and a memory controller that uses the same. The method includes initializing a linear feed-back shift register (LFSR) circuit in a CRC polynomial, generating CRC parity information with respect to input data to be stored in a memory device by using the LFSR circuit, and generating a CRC code with respect to the input data based on the CRC parity information, such that the initialization of the LFSR circuit is set such that a register initial value of the LFSR circuit is determined to satisfy a condition that, when data input to the LFSR circuit is first state information, the CRC parity information generated from the LFSR circuit is second state information.

Method of operating cyclic redundancy check in memory system and memory controller using the same

A hard-decision decoding method includes performing operations necessary for first updating of a check node while loading data, which is input to a decoder, to an input buffer; first updating the check node by using a result of the performing of the operations after storing data, corresponding to one codeword, to the input buffer; and performing low-density parity check (LDPC) decoding by using a result of the first updating of the check node.

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Yongin-si, South Korea

Bi-woong Chung