Samsung Electronics Co., Ltd.

Bi-O Kim

Jae-young Ahn

Ki-Hyun Hwang

Seung-hyun Lim

Phil-Ouk Nam

Chang-Woo Sun

Jin-Tae Noh

Jae-Ho Choi

Han-Mei Choi

Jin-Gyun Kim

Jung-Geun Jee

Toshiro Nakanishi

Dong-Chul Yoo

Ki-hyun Hwang

Jun-Kyu Yang

Young-jin Noh

Byong-Hyun Jang

Kwang-Min Park

Byong-Ju Kim

Jin-tae Noh

Ju-Mi Yun

Eun-Yeoung Choi

Chang-woo Sun

Tunnel insulation layer structures and methods of manufacturing the same are disclosed. The tunnel insulation layer structures may include a first tunnel insulation layer, a second tunnel insulation layer, a third tunnel insulation layer, a fourth tunnel insulation layer and a fifth tunnel insulation layer. The first tunnel insulation layer on a substrate has a first band gap energy. The second tunnel insulation layer on the first tunnel insulation layer has a second band gap energy which is lower than the first band gap energy. The third tunnel insulation layer on the second tunnel insulation layer has a third band gap energy which is higher than the second band gap energy. The fourth tunnel insulation layer on the third tunnel insulation layer has a fourth band gap energy which is lower than the third band gap energy. The fifth tunnel insulation layer on the fourth tunnel insulation layer has a fifth band gap energy which is higher than the fourth band gap energy.

Tunnel insulation layer structures, methods of manufacturing the same, and vertical memory devices including the same

A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.

Semiconductor device and method of manufacturing the same

A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

Vertical memory devices and methods of manufacturing the same

According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.

Semiconductor device including a first core pattern under a second core pattern

Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.

A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms.

Method of manufacturing semiconductor device

Growing community of inventors

Seoul, South Korea

Bi-O Kim