Taiwan Semiconductor Manufacturing Comp. Ltd.

Bi-Fen Wu

Chih-Hao Chang

Jen-Hsiang Lu

Chung-Ting Li

Chung-Ting Ko

Chi-On Chui

Huan-Just Lin

Kuei Shun Chen

Chia-Chu Liu

Hui-Chi Huang

Mu-Chi Chiang

Hsiao-Tzu Lu

Yao-Kwang Wu

A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

Method of fabricating a semiconductor device

A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Gate spacer structure of FinFET device

Semiconductor device and method of fabricating a semiconductor device

Gate spacer structure of finFET device

FinFET device and method of forming same

A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.

Field effect transistors and method of forming the same

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Taichung, Taiwan

Bi-Fen Wu